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<div class="nine columns main-col"> <div class="nine columns main-col">
<h2>Who am I?</h2> <h2>Who am I?</h2>
<p> <p>
Currently working as engineering consultant for Aquantia Corp. Always curious about technological innovations and therefore graduated in electrical engineering & computer science. Strives for a complete understanding of computers, from the lowest level—i.e., the bare integrated circuits—to the highest—i.e., user space—, and is therefore always eager to learn something new. Enjoys writing small programs in his free time, either to automate everyday problems, or simply for the sake of fun, and gets excited by the seemingly endless possibilities of Linux. Loves a good read, also on non-tech subjects like economics, anthropology, or (geo)politics. Currently a Member of Technical Staff at Aquantia Corp. Always curious about technological innovations and therefore graduated in electrical engineering & computer science. Strives for a complete understanding of computers, from the lowest level—i.e., the bare integrated circuits—to the highest—i.e., user space—, and is therefore always eager to learn something new. Enjoys writing small programs in his free time, either to automate everyday problems, or simply for the sake of fun, and gets excited by the seemingly endless possibilities of Linux. Loves a good read, also on non-tech subjects like economics, anthropology, or (geo)politics.
</p> </p>
<h2>Contact Details</h2> <h2>Contact Details</h2>
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<ul class="disc"> <ul class="disc">
<li><i>Specialization</i>: Micro- and Nanoelectronics</li> <li><i>Specialization</i>: Micro- and Nanoelectronics</li>
<li><i>Final project</i>: "<a href="https://git.dennispotter.eu/Dennis/masters-thesis/releases">Implementation and Analysis of an InfiniBand based Communication in a Real-Time Co-Simulation Framework</a>"&mdash;An analysis and subsequent implementation of the Virtual Interface Architecture Infiniband, using the OpenStack verbs, in order to achieve high throughput and minimal latency between nodes of the real-time co-simulation framework VILLASnode.</li> <li><i>Final project</i>: "<a href="https://git.dennispotter.eu/Dennis/masters-thesis/releases">Implementation and Analysis of an InfiniBand based Communication in a Real-Time Co-Simulation Framework</a>"&mdash;An analysis and subsequent implementation of the Virtual Interface Architecture Infiniband, using the OpenStack verbs, in order to achieve high throughput and minimal latency between nodes of the real-time co-simulation framework VILLASnode. (Grade: A+)</li>
<li><i>Modules included</i>: lectures on VLSI architectures, computer arithmetics, mixed analog signals, neural networks, new materials and devices in information technology, numerical device simulation, and operating systems. Lab training on VLSI design, FPGA programming in VHDL, and on the production of FeRAM cells.</li> <li><i>Modules included</i>: lectures on VLSI architectures, computer arithmetics, mixed analog signals, neural networks, new materials and devices in information technology, numerical device simulation, and operating systems. Lab training on VLSI design, FPGA programming in VHDL, and on the production of FeRAM cells.</li>
</ul> </ul>
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<p class="info">B.Sc. Electrical Engineering and Computer Science<span>&bull;</span> <p class="info">B.Sc. Electrical Engineering and Computer Science<span>&bull;</span>
<em class="date">October 2011 - September 2015</em></p> <em class="date">October 2011 - September 2015</em></p>
<ul class="disc"> <ul class="disc">
<li><i>Final project</i>: “Analysis of Concepts for Power Reduction in Arithmetic Units of MAP Decoders”&mdash;A mathematical, bit accurate implementation of a decoder in MATLAB and C++, to find techniques that will potentially reduce the switching activity (and thus the power) in the arithmetic units of the decoder.</li> <li><i>Final project</i>: “Analysis of Concepts for Power Reduction in Arithmetic Units of MAP Decoders”&mdash;A mathematical, bit accurate implementation of a decoder in MATLAB and C++, to find techniques that will potentially reduce the switching activity (and thus the power) in the arithmetic units of the decoder. (Grade: A+)</li>
</ul> </ul>
</p> </p>
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<div class="twelve columns"> <div class="twelve columns">
<h3>Aquantia Corporation</h3> <h3>Aquantia Corporation</h3>
<p class="info">Consultant<span>&bull;</span> <em class="date">August 2017 - Present</em></p> <p class="info">Member of Technical Staff<span>&bull;</span> <em class="date">December 2018 - Present</em></p>
<ul class="disc">
<li>Design of digital Ethernet logic.</li>
</ul>
<p class="info">Consultant<span>&bull;</span> <em class="date">August 2017 - November 2018</em></p>
<ul class="disc"> <ul class="disc">
<li>Development of a layer 2 Ethernet switch in SystemC. The goal was to create a transmission line model to verify functionality, which could be easily translated into synthesizable code later, using a high-level synthesis suite.</li> <li>Development of a layer 2 Ethernet switch in SystemC. The goal was to create a transmission line model to verify functionality, which could be easily translated into synthesizable code later, using a high-level synthesis suite.</li>
<li>Support and further development of the FPGA user interface and the power analysis environment which was developed during the internship.</li> <li>Support and further development of the FPGA user interface and the power analysis environment which was developed during the internship.</li>