diff --git a/index.html b/index.html index 30327fc..516df28 100755 --- a/index.html +++ b/index.html @@ -54,8 +54,7 @@ @@ -77,13 +76,11 @@ @@ -107,12 +104,12 @@

Who am I?

- Currently I am a senior engineer at Marvell Semiconductor. I have always been curious about technological innovations and therefore graduated in electrical & computer engineering. I still strive for a complete understanding of computers, from the lowest level—i.e., the bare integrated circuits—to the highest—i.e., user space—, and am therefore always eager to learn something new. I enjoy writing small programs in my free time, either to automate everyday problems, or simply for the sake of fun, and get excited by the seemingly endless possibilities of Linux. Furthermore, there is always time for a good read, also on non-tech subjects like economics, anthropology, or (geo)politics. + I am a digital IC design engineer and have always been curious about technological innovations. For that reason I graduated in electrical & computer engineering. I have always striven for a complete understanding of computers, from the lowest level—i.e., the bare integrated circuits—to the highest—i.e., user space—, and am therefore always eager to learn something new. I enjoy writing small programs in my free time, either to automate everyday problems, or simply for the sake of fun, and get excited by the seemingly endless possibilities of Linux. Furthermore, there is always time for a good read, also on non-tech subjects like economics, anthropology, or (geo)politics.

Contact Details

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Do you want to get in touch? Click here to get to the contact section of this page. There I provided my phone number, email address, PGP Key ID, Matrix ID and several other ways to reach me!

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Do you want to get in touch? Click here to get to the contact section of this page. or reach out over LinkedIn.

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Education

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RWTH Aachen University

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M.Sc. Electrical and Computer Engineering• - October 2015 - November 2018

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  • Specialization: Micro- and Nanoelectronics
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  • Final project: "Implementation and Analysis of an InfiniBand based Communication in a Real-Time Co-Simulation Framework"—An analysis and subsequent implementation of the Virtual Interface Architecture Infiniband, using the OpenStack verbs, in order to achieve high throughput and minimal latency between nodes of the real-time co-simulation framework VILLASnode. (Grade: A+)
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  • Modules included: lectures on VLSI architectures, computer arithmetics, mixed analog signals, neural networks, new materials and devices in information technology, numerical device simulation, and operating systems. Lab training on VLSI design, FPGA programming in VHDL, and on the production of FeRAM cells.
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RWTH Aachen University

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B.Sc. Electrical and Computer Engineering• - October 2011 - September 2015

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  • Final project: “Analysis of Concepts for Power Reduction in Arithmetic Units of MAP Decoders”—A mathematical, bit accurate implementation of a decoder in MATLAB and C++, to find techniques that will potentially reduce the switching activity (and thus the power) in the arithmetic units of the decoder. (Grade: A+)
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Sophianum SG. in het Heuvelland

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Gymnasium• - September 2005 - July 2011

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  • Comparable to a university-preparatory school with Latin as additional language.
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Work

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Marvell Semiconductor

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Senior Engineer• September 2019 - Present

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  • Design of digital logic for an automotive Ethernet product.
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Aquantia Corporation

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Member of Technical Staff II • December 2018 - September 2019

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  • Design of digital logic for an automotive Ethernet product.
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Consultant• August 2017 - November 2018

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  • Development of a synthesizable layer 2 Ethernet switch in SystemC and evaluation of DV & synthesis capabilities of a high-level synthesis suite.
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  • Support and further development of the FPGA user interface and the power analysis environment which was developed during the internship.
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Intern • Nobember 2016 - July 2017

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  • RTL power analysis and reduction on various digital designs.
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  • Development of an intuitive GUI—written in Python, Tkinter, and C—to control an FPGA Ethernet debug tool.
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Boscafé 't Hijgend Hert

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Web developer and server administrator • April 2012 - November 2018

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  • Responsible for the restaurant's IT, the development of several websites, and the maintenance and security of their Linux based VPS.
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Headwaiter • September 2010 - October 2016

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  • Head of a team of about 8 waiters. Responsible for a smooth running of daily restaurant business.
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Chair for Electrical Engineering and Computer Systems, RWTH Aachen University

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Student Research Assistent • May 2016 - July 2016

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  • Establishment of burst-mode communication between the FPGA fabric and CPU subsystem on an Altera Cyclone V device.
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Skills

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- Below, I listed skills I acquired during my professional work or during work in my free time. Besides the skills I have listed below, I have basic - knowledge about photography and photo editting, front-end web development with HTML5, CSS, and JavaScript, and back-end webdevelopment with PHP/Python and MySQL/PostgreSQL. -

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  • (System)Verilog
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  • SystemC
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  • Matlab
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  • Linux Server configuration
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  • FPGA
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