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%	SECTION TITLE
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\cvsection{Education}


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%	CONTENT
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\vspace{-3.5mm}
\begin{cventries}

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  \cventrydouble
    {M.Sc. Electrical Engineering, Information Technology, \& Computer Engineering} % Degree
    {RWTH Aachen University} % Institution
    {Aachen (D)} % Location
    {Oct. 2015 - Nov. 2018} % Date(s)
    {
      \begin{cvitems} % Description(s) bullet points
        \item \textit{Specialization}: Micro- and Nanoelectronics
        \item \textit{Final project}: ``Implementation and Analysis of RDMA Communication in a Real-Time Co-Simulation Framework"---An analysis and subsequent implementation of the Virtual Interface Architecture Infiniband, using the OpenStack verbs, in order to achieve high throughput and minimal latency between nodes of the real-time co-simulation framework VILLASnode.
        \item \textit{Modules included}: lectures on VLSI architectures, computer arithmetics, mixed analog signals, neural networks, new materials and devices in information technology, numerical device simulation, and operating systems. Lab trainings on full custom design, FPGA development, and on the production of FeRAM cells. 
      \end{cvitems}
    }
    {B.Sc. Electrical Engineering, Information Technology, \& Computer Engineering} % Degree
    {Aachen (D)} % Location
    {Oct. 2011 - Sept. 2015} % Date(s)
    {
      \begin{cvitems} % Description(s) bullet points
        \item \textit{Final project}: ``Analysis of Concepts for Power Reduction in Arithmetic Units of MAP Decoders”---A mathematical, bit accurate implementation of a decoder in MATLAB and C++, to find techniques that will potentially reduce the switching activity (and thus the power) in the arithmetic units of the decoder. 
      \end{cvitems}
    }

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  \cventry
  {Gymnasium (Comparable to a university-preparatory school with Latin as additional language.)} % Degree
    {Sophianum SG. in het Heuvelland} % Institution
    {Gulpen (NL)} % Location
    {Sept. 2005 - July. 2011} % Date(s)
    {
    }

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\end{cventries}
