103 lines
5.8 KiB
TeX
103 lines
5.8 KiB
TeX
%-------------------------------------------------------------------------------
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% SECTION TITLE
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%-------------------------------------------------------------------------------
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\cvsection{Work Experience}
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%-------------------------------------------------------------------------------
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% CONTENT
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%-------------------------------------------------------------------------------
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\vspace{-1.5mm}
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\begin{cventries}
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%---------------------------------------------------------
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\cventry
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{Senior Staff Digital Design Engineer} % Job title
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{Marvell Semiconductor} % Organization
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{Santa Clara (USA)} % Location
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{Jul. 2021 - Present} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Owning a digital subsystem that provides MACsec (IEEE 802.3AE), PTP (IEEE 1588/IEEE 802.1AS), and MAC functionalities.
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\item Maintaining \& improving the proprietary Logic Analyser Module (LAM) hardware and software. Debugging silicon issues on various products with help of the proprietary LAM.
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\item Improving \& extending the previously designed front-end methodology. This includes, i.a., replacing underperforming EDA tools, using novel version control management techniques to improve user usability \& efficiency, adding automated regression tests to increase the (early) detection of bugs.
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\item Reviewing digital signal processing (DSP) hardware in a coherent optical DSP chip and developing the firmware for said hardware.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventry
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{Staff Digital Design Engineer} % Job title
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{Marvell Semiconductor} % Organization
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{Aachen (D)} % Location
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{Oct. 2019 - Jul. 2021} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Owning a digital subsystem that provides MACsec (IEEE 802.3AE), PTP (IEEE 1588/IEEE 802.1AS), and MAC functionalities.
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\item Co-architecting and implementing a CSI module. This includes the encapsulation of pseudo-CSI2-packets into Ethernet packets with a configurable Ethernet/IP/UDP/AVTP header at the Rx-side of the block, and decapsulation and reordering of those packets at a Tx-side.
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\item Creating software to extract signals from a proprietary Logic Analyser Module and subsequently translating it to a VCD file that can be interpreted by any waveform viewer.
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\item Developing a script to automatically resolve congestion issues and Lint warnings in auto-generated register files.
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\item Debugging AHB bus issues in full chip simulations.
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\item Setting up a methodology for all front-end activity. This includes, i.a., the directory structure, version control management, regression management, RTL coding guidelines, and design libraries. Furthermore, convenient wrapper scripts that seemingly integrate in the flow for Cadence Joules, Spyglass Lint, Mentor CDC, Agnisys idsbatch, Cadence Conformal, and TSMC memories were written.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventrytriple
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{Member of Technical Staff II} % Job title
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{Aquantia Corp.} % Organization
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{Aachen (D)} % Location
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{Dec. 2018 - Sept. 2019} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Designing a store \& forward Ethernet switch with a dynamic CAM, FRER (de)duplication, and seperate lanes for high- and low priority traffic.
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\item Creating a proprietary Logic Analyser Module to extract signals from the silicon chip. This includes cyclic buffering, triggering on (maskable) patterns, filtering (maskable) patterns, and compression.
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\item Developing a Python script to pre-process (hierarchical) Verilog Manifest files and sanity checking the included files.
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\end{cvitems}
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}
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{Contractor} % Job title
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{Aachen (D)} % Location
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{Aug. 2017 - Nov. 2018} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Developing a synthesizable layer 2 Ethernet switch in SystemC and evaluating DV \& synthesis capabilities of a high-level synthesis suite.
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\item Providing support for the FPGA GUI and the power analysis environment that was developed during the internship.
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\end{cvitems}
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}
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{Intern} % Job title
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{San José (USA)} % Location
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{Nov. 2016 - July. 2017} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item RTL power analysis and reduction on various digital designs using Ansys' PowerArtist.
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\item Developing an intuitive GUI—written in Python, Tkinter, and C—to control an FPGA Ethernet debug tool.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventry
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{Web developer and server administrator} % Job title
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{Boscafé 't Hijgend Hert} % Organization
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{Vijlen (NL)} % Location
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{Apr. 2012 - Mar. 2018} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Boscafé 't Hijgend Hert is a popular restaurant (500+ seats) \& tourist destination in the south of the Netherlands. Responsibilities included the restaurant's IT (including POS systems), the development of several websites, and the maintenance and security of their Linux based VPS.
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\end{cvitems}
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}
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%---------------------------------------------------------
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\cventry
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{Student Research Assistent} % Job title
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{Chair for Electrical Engineering and Computer Systems, RWTH Aachen University} % Organization
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{Aachen (D)} % Location
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{May. 2016 - July. 2016} % Date(s)
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{
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\begin{cvitems} % Description(s) of tasks/responsibilities
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\item Establishment of burst-mode communication between the FPGA fabric and CPU subsystem, over AXI and/or DDR interface on Altera Cyclone V devices.
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\end{cvitems}
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}
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\end{cventries}
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