mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-23 07:08:39 +00:00
141 lines
3.8 KiB
Python
141 lines
3.8 KiB
Python
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from enum import Enum
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import math
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import cocotb
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from cocotb.triggers import Timer, RisingEdge
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# TODO: Does not yet implement HREADY_OUT == 0
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# TODO: Add support for HRESP (and throw error if HRESP occurs)
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class HTRANS(Enum):
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IDLE = 0
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BUSY = 1
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NONSEQ = 2
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SEQ = 3
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class AMBA3AHBLiteDriver:
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"""Wraps up a collection of functions to drive an AMBA3AHBLite Bus.
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This is not an extensive set of features and merely enough to test
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out SRDL2SV registers.
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"""
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def __init__(self, dut, nbytes: int):
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self._nbytes = nbytes
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self._dut = dut
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@cocotb.coroutine
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async def reset(self, time: int = 10):
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"""Resets bus for a given amount of time"""
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self._dut.HRESETn <= 0
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await Timer(time, units='ns')
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await RisingEdge(self._dut.clk)
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self._dut.HRESETn <= 1
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@cocotb.coroutine
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async def write(self, address: int, value: int, nbytes = None, step_size = None):
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if not nbytes:
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nbytes = self._nbytes
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if not step_size:
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if (step_size := address % self._nbytes) == 0:
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step_size = self._nbytes
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# Dictionary to return address/value pairs
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write_dict = {}
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# Start counting bytes
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nbytes_cnt = 0
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# Initiate write
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self._dut.HSEL <= 1
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self._dut.HWRITE <= 1
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self._dut.HADDR <= address
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self._dut.HTRANS <= HTRANS.NONSEQ.value
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self._dut.HSIZE <= int(math.log2(step_size))
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await RisingEdge(self._dut.clk)
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while True:
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# Save address from previous phase
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previous_address = hex(self._dut.HADDR.value)
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# Set data for dataphase
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self._dut.HWDATA <= (value >> (nbytes_cnt * 8))
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# Check if we are done in next phase
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if (nbytes_cnt := nbytes_cnt + step_size) >= nbytes:
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self._dut.HTRANS <= HTRANS.IDLE.value
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else:
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# Update address
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self._dut.HADDR <= self._dut.HADDR.value + step_size
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# Wait for next clock cycle
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await RisingEdge(self._dut.clk)
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# Save into dictionary
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write_dict[previous_address] = hex(self._dut.HWDATA.value)
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if nbytes_cnt >= nbytes:
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break
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self._dut.HWRITE <= 0
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self._dut.HSEL <= 0
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await RisingEdge(self._dut.clk)
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return write_dict
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@cocotb.coroutine
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async def read(self, address: int, nbytes = None, step_size = None):
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if not nbytes:
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nbytes = self._nbytes
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if not step_size:
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if (step_size := address % self._nbytes) == 0:
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step_size = self._nbytes
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# Dictionary to return address/value pairs
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read_dict = {}
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# Start counting bytes
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nbytes_cnt = 0
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# Initiate read
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self._dut.HSEL <= 1
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self._dut.HWRITE <= 0
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self._dut.HADDR <= address
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self._dut.HTRANS <= HTRANS.NONSEQ.value
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self._dut.HSIZE <= int(math.log2(step_size))
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await RisingEdge(self._dut.clk)
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while True:
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# Save address from previous phase
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previous_address = hex(self._dut.HADDR.value)
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# Check if we are done in next phase
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if (nbytes_cnt := nbytes_cnt + step_size) >= nbytes:
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self._dut.HTRANS <= HTRANS.IDLE.value
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else:
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# Update address
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self._dut.HADDR <= self._dut.HADDR.value + step_size
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# Wait for next clock cycle
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await RisingEdge(self._dut.clk)
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# Save into dictionary
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read_dict[previous_address] = hex(self._dut.HRDATA.value)
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if nbytes_cnt >= nbytes:
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break
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self._dut.HTRANS <= HTRANS.IDLE.value
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self._dut.HSEL <= 0
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await RisingEdge(self._dut.clk)
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return read_dict
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