srdl2sv/tests/systemrdl/simple_rw_reg.rdl

addrmap simple_rw_reg {
    reg {
        regwidth = 32;
        field {sw=rw; hw=rw; we;} f1 [15:0];
        field {sw=rw; hw=rw; we;} f2 [31:16];
    } register_0 [2];
};
Add directory that will contain SystemRDL files for tests 2021-09-14 05:09:04 +00:00			`addrmap simple_rw_reg {`
			`reg {`
Fix simple_rw_reg.rdl so that the test passes The register was defined as a 64-bit register but the test was written under the assumption it's a 32-bit register. Furthermore, the hardware write-enable flag had to be set since all values would otherwise be overwritten immediately. 2021-10-24 22:43:44 +00:00			`regwidth = 32;`
			`field {sw=rw; hw=rw; we;} f1 [15:0];`
			`field {sw=rw; hw=rw; we;} f2 [31:16];`
Add directory that will contain SystemRDL files for tests 2021-09-14 05:09:04 +00:00			`} register_0 [2];`
			`};`