diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py
index 77f2448..1d59f45 100644
--- a/srdl2sv/components/addrmap.py
+++ b/srdl2sv/components/addrmap.py
@@ -176,19 +176,19 @@ class AddrMap(Component):
                 AddrMap.templ_dict['read_mux'],
                 {'list_of_cases':
                     '\n'.join([
-                        AddrMap.templ_dict['list_of_mux_cases']['rtl']
+                        AddrMap.templ_dict['default_mux_case']['rtl'],
+                        *[AddrMap.templ_dict['list_of_mux_cases']['rtl']
                             .format(x[0][1]+x[1][0],
                                     ''.join(
                                         [x[0][0],
                                          x[1][1]])) for y in self.children.values() \
                                                         for x in y.create_mux_string()
-                        ])
+                        ]
+                    ])
                 }
             )
         )
 
-
-
     def __add_signal_instantiation(self):
         dict_list = [(key, value) for (key, value) in self.get_signals(True).items()]
         signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
diff --git a/srdl2sv/components/templates/addrmap.yaml b/srdl2sv/components/templates/addrmap.yaml
index 7375a0b..1d25554 100644
--- a/srdl2sv/components/templates/addrmap.yaml
+++ b/srdl2sv/components/templates/addrmap.yaml
@@ -58,6 +58,9 @@ read_mux:
       {list_of_cases}
       endcase
       end
+default_mux_case:
+    rtl: |-
+        default: sw_rd_bus = 0;
 list_of_mux_cases:
     rtl: |-
         32'd{}: sw_rd_bus = {};