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Fix bug with static values for saturate/threshold values

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This commit is contained in:
Dennis Potter 2021-11-06 18:24:42 -07:00
parent b44813e0c5
commit 17c1b9b9a0
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 23 additions and 17 deletions
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38
srdl2sv/components/field.py
View File

@ -262,48 +262,54 @@ class Field(Component):
self.rtl_footer.append(Field.templ_dict['counter_comment']['rtl']) self.rtl_footer.append(Field.templ_dict['counter_comment']['rtl'])
# Determine saturation values # Determine saturation values
if isinstance(self.obj.get_property('incrsaturate'), bool): if isinstance(saturate := self.obj.get_property('incrsaturate'), bool):
if self.obj.get_property('incrsaturate'): if saturate:
incr_sat_value = f"{self.obj.width}'d{2**self.obj.width-1}" incr_sat_value = f"{self.obj.width}'d{2**self.obj.width-1}"
overflow_value = incr_sat_value overflow_value = incr_sat_value
else: else:
incr_sat_value = False incr_sat_value = False
overflow_value = 2**self.obj.width-1 overflow_value = 2**self.obj.width-1
elif isinstance(saturate, int):
incr_sat_value = f"{self.obj.width}'d{saturate}"
underflow_value = incr_sat_value
else: else:
incr_sat_value = self.get_signal_name( incr_sat_value = self.get_signal_name(saturate)
self.obj.get_property('incrsaturate'))
overflow_value = incr_sat_value overflow_value = incr_sat_value
if isinstance(self.obj.get_property('decrsaturate'), bool): if isinstance(saturate := self.obj.get_property('decrsaturate'), bool):
if self.obj.get_property('decrsaturate'): if saturate:
decr_sat_value = f"{self.obj.width}'d0" decr_sat_value = f"{self.obj.width}'d0"
underflow_value = decr_sat_value underflow_value = decr_sat_value
else: else:
decr_sat_value = False decr_sat_value = False
underflow_value = 0 underflow_value = 0
elif isinstance(saturate, int):
decr_sat_value = f"{self.obj.width}'d{saturate}"
underflow_value = decr_sat_value
else: else:
decr_sat_value = self.get_signal_name( decr_sat_value = self.get_signal_name(saturate)
self.obj.get_property('decrsaturate'))
underflow_value = decr_sat_value underflow_value = decr_sat_value
# Determine threshold values # Determine threshold values
if isinstance(self.obj.get_property('incrthreshold'), bool): if isinstance(threshold := self.obj.get_property('incrthreshold'), bool):
if self.obj.get_property('incrthreshold'): if threshold:
incr_thr_value = f"{self.obj.width}'d{2**self.obj.width-1}" incr_thr_value = f"{self.obj.width}'d{2**self.obj.width-1}"
else: else:
incr_thr_value = False incr_thr_value = False
elif isinstance(threshold, int):
incr_thr_value = f"{self.obj.width}'d{threshold}"
else: else:
incr_thr_value = self.get_signal_name( incr_thr_value = self.get_signal_name(threshold)
self.obj.get_property('incrthreshold'))
if isinstance(self.obj.get_property('decrthreshold'), bool): if isinstance(threshold := self.obj.get_property('decrthreshold'), bool):
if self.obj.get_property('decrthreshold'): if threshold:
decr_thr_value = f"{self.obj.width}'d{2**self.obj.width-1}" decr_thr_value = f"{self.obj.width}'d{2**self.obj.width-1}"
else: else:
decr_thr_value = False decr_thr_value = False
elif isinstance(threshold, int):
decr_thr_value = f"{self.obj.width}'d{threshold}"
else: else:
decr_thr_value = self.get_signal_name( decr_thr_value = self.get_signal_name(threshold)
self.obj.get_property('decrthreshold'))
# Determine with what value the counter is incremented # Determine with what value the counter is incremented
# According to the spec, the incrvalue/decrvalue default to '1' # According to the spec, the incrvalue/decrvalue default to '1'

2
srdl2sv/components/templates/fields.yaml
View File

@ -397,7 +397,7 @@ counter_incr_thr:
signal_type: 'logic' signal_type: 'logic'
counter_decr_thr: counter_decr_thr:
rtl: |- rtl: |-
assign {path}_decr_thr{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) <= {{1'b0, {sat_value}}} + ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}}) ; assign {path}_decr_thr{genvars} = {{1'b0, {path}_q{genvars}}} + ({{{width_plus_1}{{{path}_incr}}}} & {{{incr_sat_zero_pad}{path}_incr_val}}) <= {{1'b0, {thr_value}}} + ({{{width_plus_1}{{{path}_decr}}}} & {{{decr_sat_zero_pad}{path}_decr_val}}) ;
output_ports: output_ports:
- name: '{path}_decr_thr' - name: '{path}_decr_thr'
signal_type: 'logic' signal_type: 'logic'