From 1d50b2b45739c5a01feace16e3e34c0b2f348af4 Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Tue, 29 Jun 2021 00:14:51 +0200
Subject: [PATCH] Add incrthreshold/decrthreshold support

It is still not possible to assign overflow/threshold signals to any
input of a different register!
---
 srdl2sv/components/field.py              | 49 +++++++++++++++++++++++-
 srdl2sv/components/templates/fields.yaml | 16 ++++++++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/srdl2sv/components/field.py b/srdl2sv/components/field.py
index bcf1874..1ec9088 100644
--- a/srdl2sv/components/field.py
+++ b/srdl2sv/components/field.py
@@ -214,7 +214,7 @@ class Field(Component):
 
             self.rtl_footer.append(Field.templ_dict['counter_comment']['rtl'])
 
-            # Determine saturation values and add appropriate RTL
+            # Determine saturation values
             if isinstance(self.obj.get_property('incrsaturate'), bool):
                 if self.obj.get_property('incrsaturate'):
                     incr_sat_value = 2**self.obj.width-1
@@ -237,6 +237,23 @@ class Field(Component):
                 decr_sat_value = self.obj.get_property('decrsaturate')
                 underflow_value = decr_sat_value
 
+            # Determine threshold values
+            if isinstance(self.obj.get_property('incrthreshold'), bool):
+                if self.obj.get_property('incrthreshold'):
+                    incr_thr_value = 2**self.obj.width-1
+                else:
+                    incr_thr_value = False
+            else:
+                incr_thr_value = self.obj.get_property('incrthreshold')
+
+            if isinstance(self.obj.get_property('decrthreshold'), bool):
+                if self.obj.get_property('decrthreshold'):
+                    decr_thr_value = 2**self.obj.width-1
+                else:
+                    decr_thr_value = False
+            else:
+                decr_thr_value = self.obj.get_property('decrthreshold')
+
             # Determine with what value the counter is incremented
             # According to the spec, the incrvalue/decrvalue default to '1'
             obj_incr_value = self.obj.get_property('incrvalue')
@@ -508,6 +525,36 @@ class Field(Component):
                     )
                 )
 
+            # Handle threshold values
+            if incr_thr_value or decr_thr_value:
+                self.rtl_footer.append(Field.templ_dict['counter_thr_comment']['rtl'])
+
+            if incr_thr_value:
+                self.rtl_footer.append(
+                    self.process_yaml(
+                        Field.templ_dict['counter_incr_thr'],
+                        {'path': self.path_underscored,
+                         'genvars': self.genvars_str,
+                         'incr_width': incr_width,
+                         'decr_width': decr_width,
+                         'thr_value': incr_thr_value,
+                        }
+                    )
+                )
+
+            if decr_thr_value:
+                self.rtl_footer.append(
+                    self.process_yaml(
+                        Field.templ_dict['counter_decr_thr'],
+                        {'path': self.path_underscored,
+                         'genvars': self.genvars_str,
+                         'incr_width': incr_width,
+                         'decr_width': decr_width,
+                         'thr_value': decr_thr_value,
+                        }
+                    )
+                )
+
             # Handle overflow & underflow signals
             if self.obj.get_property('overflow'):
                 self.rtl_footer.append(
diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml
index 7aafbea..c2b320b 100644
--- a/srdl2sv/components/templates/fields.yaml
+++ b/srdl2sv/components/templates/fields.yaml
@@ -344,6 +344,22 @@ counter_decr_sat_tied:
     signals:
         - name: '{path}_decr_sat'
           signal_type: 'logic'
+counter_thr_comment:
+    rtl: |-
+
+        // Define threshold signals (similar to overflow, but for a user specified value)
+counter_incr_thr:
+    rtl: |-
+        assign {path}_incr_thr{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {thr_value};
+    output_ports:
+        - name: '{path}_incr_thr'
+          signal_type: 'logic'
+counter_decr_thr:
+    rtl: |-
+        assign {path}_decr_thr{genvars} = {path}_q{genvars} + ({{{incr_width}{{{path}_incr}}}} & {path}_incr_val) - ({{{decr_width}{{{path}_decr}}}} & {path}_decr_val) > {thr_value};
+    output_ports:
+        - name: '{path}_decr_thr'
+          signal_type: 'logic'
 counter_overflow:
     rtl: |-