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Fix compile error because of multiple else branches

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This is caused by register access properties that don't have a
condition. As soon as such a property is encountered, no more branches
shall be added to that register.
This commit is contained in:
Dennis Potter 2021-06-03 12:53:39 +02:00
parent 5d76830931
commit 22f88efcd8
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 37 additions and 27 deletions
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64
srdl2sv/components/field.py
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@ -140,7 +140,7 @@ class Field(Component):
def __process_variables(self, obj: FieldNode, array_dimensions: list, glbl_settings: dict): def __process_variables(self, obj: FieldNode, array_dimensions: list, glbl_settings: dict):
# Create full name # Create full name
self.path_wo_field = '.'.join(self.path.split('.', -1)[0:-1]) self.path_wo_field = '__'.join(self.path.split('.', -1)[0:-1])
# Save dimensions of unpacked dimension # Save dimensions of unpacked dimension
self.array_dimensions = array_dimensions self.array_dimensions = array_dimensions
@ -247,50 +247,54 @@ class Field(Component):
# - hw_write --> write access for the hardware interface # - hw_write --> write access for the hardware interface
# - sw_write --> write access for the software interface # - sw_write --> write access for the software interface
# #
access_rtl = dict([]) access_rtl = dict()
# Define hardware access (if applicable) # Define hardware access (if applicable)
access_rtl['hw_write'] = []
if self.hw_access in (AccessType.rw, AccessType.w): if self.hw_access in (AccessType.rw, AccessType.w):
if self.we_or_wel: if self.we_or_wel:
access_rtl['hw_write'].append( access_rtl['hw_write'] = ([
Field.templ_dict['hw_access_we_wel']['rtl'].format( Field.templ_dict['hw_access_we_wel']['rtl'].format(
negl = '!' if self.obj.get_property('wel') else '', negl = '!' if self.obj.get_property('wel') else '',
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str)) genvars = self.genvars_str)
],
False)
else: else:
access_rtl['hw_write'].append( access_rtl['hw_write'] = ([
Field.templ_dict['hw_access_no_we_wel']['rtl']) Field.templ_dict['hw_access_no_we_wel']['rtl']
],
True)
access_rtl['hw_write'].append( access_rtl['hw_write'][0].append(
Field.templ_dict['hw_access_field']['rtl'].format( Field.templ_dict['hw_access_field']['rtl'].format(
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str)) genvars = self.genvars_str))
self.yaml_signals_to_list(Field.templ_dict['hw_access_field']) self.yaml_signals_to_list(Field.templ_dict['hw_access_field'])
else:
access_rtl['hw_write'] = ([], False)
# Define software access (if applicable) # Define software access (if applicable)
access_rtl['sw_write'] = [] access_rtl['sw_write'] = ([], False)
if self.sw_access in (AccessType.rw, AccessType.w): if self.sw_access in (AccessType.rw, AccessType.w):
swwe = self.obj.get_property('swwe') swwe = self.obj.get_property('swwe')
swwel = self.obj.get_property('swwel') swwel = self.obj.get_property('swwel')
if isinstance(swwe, (FieldNode, SignalNode)): if isinstance(swwe, (FieldNode, SignalNode)):
access_rtl['sw_write'].append( access_rtl['sw_write'][0].append(
Field.templ_dict['sw_access_field_swwe']['rtl'].format( Field.templ_dict['sw_access_field_swwe']['rtl'].format(
path_wo_field = self.path_wo_field, path_wo_field = self.path_wo_field,
genvars = self.genvars_str, genvars = self.genvars_str,
swwe = Component.get_signal_name(swwe))) swwe = Component.get_signal_name(swwe)))
elif isinstance(swwel, (FieldNode, SignalNode)): elif isinstance(swwel, (FieldNode, SignalNode)):
access_rtl['sw_write'].append( access_rtl['sw_write'][0].append(
Field.templ_dict['sw_access_field_swwel']['rtl'].format( Field.templ_dict['sw_access_field_swwel']['rtl'].format(
path_wo_field = self.path_wo_field, path_wo_field = self.path_wo_field,
genvars = self.genvars_str, genvars = self.genvars_str,
swwel = Component.get_signal_name(swwel))) swwel = Component.get_signal_name(swwel)))
else: else:
access_rtl['sw_write'].append( access_rtl['sw_write'][0].append(
Field.templ_dict['sw_access_field']['rtl'].format( Field.templ_dict['sw_access_field']['rtl'].format(
path_wo_field = self.path_wo_field, path_wo_field = self.path_wo_field,
genvars = self.genvars_str)) genvars = self.genvars_str))
@ -302,7 +306,7 @@ class Field(Component):
if onwrite == OnWriteType.wuser: if onwrite == OnWriteType.wuser:
self.logger.warning("The OnReadType.wuser is not yet supported!") self.logger.warning("The OnReadType.wuser is not yet supported!")
elif onwrite in (OnWriteType.wclr, OnWriteType.wset): elif onwrite in (OnWriteType.wclr, OnWriteType.wset):
access_rtl['sw_write'].append( access_rtl['sw_write'][0].append(
Field.templ_dict[str(onwrite)]['rtl'].format( Field.templ_dict[str(onwrite)]['rtl'].format(
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str, genvars = self.genvars_str,
@ -312,7 +316,7 @@ class Field(Component):
else: else:
# If field spans multiple bytes, every byte shall have a seperate enable! # If field spans multiple bytes, every byte shall have a seperate enable!
for j, i in enumerate(range(self.lsbyte, self.msbyte+1)): for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
access_rtl['sw_write'].append( access_rtl['sw_write'][0].append(
Field.templ_dict[str(onwrite)]['rtl'].format( Field.templ_dict[str(onwrite)]['rtl'].format(
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str, genvars = self.genvars_str,
@ -325,7 +329,7 @@ class Field(Component):
# Normal write # Normal write
# If field spans multiple bytes, every byte shall have a seperate enable! # If field spans multiple bytes, every byte shall have a seperate enable!
for j, i in enumerate(range(self.lsbyte, self.msbyte+1)): for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
access_rtl['sw_write'].append( access_rtl['sw_write'][0].append(
Field.templ_dict['sw_access_byte']['rtl'].format( Field.templ_dict['sw_access_byte']['rtl'].format(
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str, genvars = self.genvars_str,
@ -335,16 +339,16 @@ class Field(Component):
msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1), msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1),
field_w = str(8 if i != self.msbyte else self.obj.width-(8*j)))) field_w = str(8 if i != self.msbyte else self.obj.width-(8*j))))
access_rtl['sw_write'].append("end") access_rtl['sw_write'][0].append("end")
onread = self.obj.get_property('onread') onread = self.obj.get_property('onread')
access_rtl['sw_read'] = [] access_rtl['sw_read'] = ([], False)
if self.sw_access in (AccessType.rw, AccessType.r) and onread: if self.sw_access in (AccessType.rw, AccessType.r) and onread:
if onread == OnReadType.ruser: if onread == OnReadType.ruser:
self.logger.warning("The OnReadType.ruser is not yet supported!") self.logger.warning("The OnReadType.ruser is not yet supported!")
else: else:
access_rtl['sw_read'].append( access_rtl['sw_read'][0].append(
Field.templ_dict[str(onread)]['rtl'].format( Field.templ_dict[str(onread)]['rtl'].format(
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str, genvars = self.genvars_str,
@ -354,19 +358,20 @@ class Field(Component):
# Add singlepulse property # Add singlepulse property
if self.obj.get_property('singlepulse'): if self.obj.get_property('singlepulse'):
access_rtl['singlepulse'] = [ access_rtl['singlepulse'] = ([
Field.templ_dict['singlepulse']['rtl'].format( Field.templ_dict['singlepulse']['rtl'].format(
path = self.path_underscored, path = self.path_underscored,
genvars = self.genvars_str) genvars = self.genvars_str)
] ],
True)
else: else:
access_rtl['singlepulse'] = [] access_rtl['singlepulse'] = ([], False)
# Define else # Define else
access_rtl['else'] = ["else"] access_rtl['else'] = (["else"], False)
# Add empty string # Add empty string
access_rtl[''] = [''] access_rtl[''] = ([''], False)
# Check if hardware has precedence (default `precedence = sw`) # Check if hardware has precedence (default `precedence = sw`)
if self.precedence == PrecedenceType.sw: if self.precedence == PrecedenceType.sw:
@ -386,15 +391,20 @@ class Field(Component):
# Add appropriate else # Add appropriate else
order_list_rtl = [] order_list_rtl = []
abort_set = False
for i in order_list: for i in order_list:
# Still a loop and not a list comprehension since this might # Still a loop and not a list comprehension since this might
# get longer in the future and thus become unreadable # get longer in the future and thus become unreadable
if len(access_rtl[i]) > 0: if len(access_rtl[i][0]) and not abort_set:
order_list_rtl = [*order_list_rtl, *access_rtl[i]] order_list_rtl = [*order_list_rtl, *access_rtl[i][0]]
order_list_rtl.append("else") order_list_rtl.append("else")
# Remove last pop # If he access_rtl entry has an abortion entry, do not print
# any further branches of the conditional block
abort_set = access_rtl[i][1]
# Remove last else
order_list_rtl.pop() order_list_rtl.pop()
# Chain access RTL to the rest of the RTL # Chain access RTL to the rest of the RTL