mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 03:03:35 +00:00
Fix compile error because of multiple else branches
This is caused by register access properties that don't have a condition. As soon as such a property is encountered, no more branches shall be added to that register.
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parent
5d76830931
commit
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GPG Key ID:
186A8AD440942BAF
@ -140,7 +140,7 @@ class Field(Component):
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def __process_variables(self, obj: FieldNode, array_dimensions: list, glbl_settings: dict):
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# Create full name
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self.path_wo_field = '.'.join(self.path.split('.', -1)[0:-1])
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self.path_wo_field = '__'.join(self.path.split('.', -1)[0:-1])
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# Save dimensions of unpacked dimension
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self.array_dimensions = array_dimensions
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@ -247,50 +247,54 @@ class Field(Component):
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# - hw_write --> write access for the hardware interface
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# - sw_write --> write access for the software interface
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#
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access_rtl = dict([])
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access_rtl = dict()
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# Define hardware access (if applicable)
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access_rtl['hw_write'] = []
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if self.hw_access in (AccessType.rw, AccessType.w):
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if self.we_or_wel:
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access_rtl['hw_write'].append(
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access_rtl['hw_write'] = ([
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Field.templ_dict['hw_access_we_wel']['rtl'].format(
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negl = '!' if self.obj.get_property('wel') else '',
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path = self.path_underscored,
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genvars = self.genvars_str))
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genvars = self.genvars_str)
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],
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False)
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else:
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access_rtl['hw_write'].append(
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Field.templ_dict['hw_access_no_we_wel']['rtl'])
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access_rtl['hw_write'] = ([
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Field.templ_dict['hw_access_no_we_wel']['rtl']
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],
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True)
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access_rtl['hw_write'].append(
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access_rtl['hw_write'][0].append(
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Field.templ_dict['hw_access_field']['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str))
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self.yaml_signals_to_list(Field.templ_dict['hw_access_field'])
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else:
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access_rtl['hw_write'] = ([], False)
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# Define software access (if applicable)
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access_rtl['sw_write'] = []
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access_rtl['sw_write'] = ([], False)
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if self.sw_access in (AccessType.rw, AccessType.w):
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swwe = self.obj.get_property('swwe')
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swwel = self.obj.get_property('swwel')
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if isinstance(swwe, (FieldNode, SignalNode)):
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access_rtl['sw_write'].append(
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access_rtl['sw_write'][0].append(
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Field.templ_dict['sw_access_field_swwe']['rtl'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str,
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swwe = Component.get_signal_name(swwe)))
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elif isinstance(swwel, (FieldNode, SignalNode)):
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access_rtl['sw_write'].append(
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access_rtl['sw_write'][0].append(
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Field.templ_dict['sw_access_field_swwel']['rtl'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str,
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swwel = Component.get_signal_name(swwel)))
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else:
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access_rtl['sw_write'].append(
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access_rtl['sw_write'][0].append(
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Field.templ_dict['sw_access_field']['rtl'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str))
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@ -302,7 +306,7 @@ class Field(Component):
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if onwrite == OnWriteType.wuser:
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self.logger.warning("The OnReadType.wuser is not yet supported!")
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elif onwrite in (OnWriteType.wclr, OnWriteType.wset):
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access_rtl['sw_write'].append(
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access_rtl['sw_write'][0].append(
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Field.templ_dict[str(onwrite)]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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@ -312,7 +316,7 @@ class Field(Component):
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else:
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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access_rtl['sw_write'][0].append(
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Field.templ_dict[str(onwrite)]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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@ -325,7 +329,7 @@ class Field(Component):
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# Normal write
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# If field spans multiple bytes, every byte shall have a seperate enable!
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for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
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access_rtl['sw_write'].append(
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access_rtl['sw_write'][0].append(
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Field.templ_dict['sw_access_byte']['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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@ -335,16 +339,16 @@ class Field(Component):
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msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1),
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field_w = str(8 if i != self.msbyte else self.obj.width-(8*j))))
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access_rtl['sw_write'].append("end")
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access_rtl['sw_write'][0].append("end")
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onread = self.obj.get_property('onread')
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access_rtl['sw_read'] = []
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access_rtl['sw_read'] = ([], False)
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if self.sw_access in (AccessType.rw, AccessType.r) and onread:
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if onread == OnReadType.ruser:
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self.logger.warning("The OnReadType.ruser is not yet supported!")
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else:
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access_rtl['sw_read'].append(
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access_rtl['sw_read'][0].append(
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Field.templ_dict[str(onread)]['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str,
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@ -354,19 +358,20 @@ class Field(Component):
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# Add singlepulse property
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if self.obj.get_property('singlepulse'):
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access_rtl['singlepulse'] = [
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access_rtl['singlepulse'] = ([
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Field.templ_dict['singlepulse']['rtl'].format(
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path = self.path_underscored,
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genvars = self.genvars_str)
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]
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],
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True)
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else:
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access_rtl['singlepulse'] = []
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access_rtl['singlepulse'] = ([], False)
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# Define else
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access_rtl['else'] = ["else"]
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access_rtl['else'] = (["else"], False)
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# Add empty string
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access_rtl[''] = ['']
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access_rtl[''] = ([''], False)
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# Check if hardware has precedence (default `precedence = sw`)
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if self.precedence == PrecedenceType.sw:
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@ -386,15 +391,20 @@ class Field(Component):
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# Add appropriate else
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order_list_rtl = []
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abort_set = False
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for i in order_list:
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# Still a loop and not a list comprehension since this might
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# get longer in the future and thus become unreadable
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if len(access_rtl[i]) > 0:
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order_list_rtl = [*order_list_rtl, *access_rtl[i]]
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if len(access_rtl[i][0]) and not abort_set:
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order_list_rtl = [*order_list_rtl, *access_rtl[i][0]]
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order_list_rtl.append("else")
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# Remove last pop
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# If he access_rtl entry has an abortion entry, do not print
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# any further branches of the conditional block
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abort_set = access_rtl[i][1]
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# Remove last else
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order_list_rtl.pop()
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# Chain access RTL to the rest of the RTL
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