From 240fba8e120e61df00e5ae6bf9357d6bc0342ce3 Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Sun, 12 Sep 2021 19:37:30 -0700
Subject: [PATCH] Resolve bug for addrmaps without any genvars

In this case, there would be a line with `genvars ;`. This is not
compilable by SystemVerilog compilers.
---
 srdl2sv/components/addrmap.py | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py
index 62038be..738d2c9 100644
--- a/srdl2sv/components/addrmap.py
+++ b/srdl2sv/components/addrmap.py
@@ -264,13 +264,16 @@ class AddrMap(Component):
 
 
     def __append_genvars(self):
-        genvars = ''.join([
-            '\ngenvar ',
-            ', '.join([chr(97+i) for i in range(self.get_max_dim_depth())]),
-            ';\n'
-            ])
+        genvars = ', '.join([chr(97+i) for i in range(self.get_max_dim_depth())])
 
-        self.rtl_header.append(genvars)
+        if genvars:
+            genvars_instantiation = ''.join([
+                '\ngenvar ',
+                genvars,
+                ';\n'
+                ])
+
+            self.rtl_header.append(genvars_instantiation)
 
     def get_package_names(self) -> set():
         names = set()