diff --git a/README.md b/README.md index 5812311..669c45d 100644 --- a/README.md +++ b/README.md @@ -81,8 +81,8 @@ The following bus protocols are planned at this point: # Help function A comprehensive help function of the tool can be invoked by running `srdl2sv --help`. ``` -usage: main.py [-h] [-b {amba3ahblite}] [-c DESCRIPTIONS] - [-d SEARCH_PATHS [SEARCH_PATHS ...]] [-e] +usage: srdl2sv [-h] [-a ADDRESS_WIDTH] [-b {simple,amba3ahblite}] + [-c DESCRIPTIONS] [-d SEARCH_PATHS [SEARCH_PATHS ...]] [-e] [--file_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}] [--stream_log_level {DEBUG,INFO,WARNING,ERROR,CRITICAL,NONE}] [--no_byte_enable] [-o OUT_DIR] [-r] [--real_tabs] @@ -96,10 +96,15 @@ positional arguments: optional arguments: -h, --help show this help message and exit - -b {amba3ahblite}, --bus {amba3ahblite} + -a ADDRESS_WIDTH, --address_width ADDRESS_WIDTH + Set the address width of the register space. For some + protocols, the default as described in the + specification is used. (default: 32) + -b {simple,amba3ahblite}, --bus {simple,amba3ahblite} Set the bus protocol that shall be used by software to - ', communicate with the registers. (default: - amba3ahblite) + communicate with the registers. If just a simple + interface to the registers is needed, use the 'simple' + protocol. (default: amba3ahblite) -c DESCRIPTIONS, --descriptions DESCRIPTIONS Include descriptions of addrmaps (+16), regfiles (+8), memories (+4) registers (+2), and fields (+1) in RTL. diff --git a/srdl2sv/cli/cli.py b/srdl2sv/cli/cli.py index f4ae06e..7c6ab67 100644 --- a/srdl2sv/cli/cli.py +++ b/srdl2sv/cli/cli.py @@ -20,13 +20,24 @@ class CliArguments(): self.parser = argparse.ArgumentParser( description="SystemRDL 2 SystemVerilog compiler") + self.parser.add_argument( + "-a", + "--address_width", + default=32, + type=int, + help="Set the address width of the register space. For some \ + protocols, the default as described in the specification \ + is used. (default: %(default)s)") + self.parser.add_argument( "-b", "--bus", - choices=['amba3ahblite'], + choices=['simple', 'amba3ahblite'], default='amba3ahblite', - help="Set the bus protocol that shall be used by software to ',\ - communicate with the registers. (default: %(default)s)") + help="Set the bus protocol that shall be used by software to \ + communicate with the registers. If just a simple interface \ + to the registers is needed, use the 'simple' protocol. \ + (default: %(default)s)") self.parser.add_argument( "-c", @@ -163,8 +174,15 @@ class CliArguments(): config['bus'] = args.bus config['list_args'].append(f"Register Bus Type: {config['bus']}") + # Address width if args.bus == 'amba3ahblite': config['addrwidth'] = 32 + config['addrwidth_bus_spec'] = True + else: + config['addrwidth'] = args.address_width + config['addrwidth_bus_spec'] = False + + config['list_args'].append(f"Address width : {config['addrwidth']}") # Byte enables? config['no_byte_enable'] = args.no_byte_enable diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py index 97bccff..c392e53 100644 --- a/srdl2sv/components/addrmap.py +++ b/srdl2sv/components/addrmap.py @@ -293,8 +293,10 @@ class AddrMap(Component): return self._process_yaml( self.widget_templ_dict['module_instantiation'], - {'bus_width': self.regwidth, + {'bus_width': self.get_regwidth(), 'no_byte_enable': 1 if self.config['no_byte_enable'] else 0, + 'addr_width': self.config['addrwidth'], + 'bus_width_byte': int(self.get_regwidth() / 8), } ) diff --git a/srdl2sv/components/widgets/srdl2sv_simple.yaml b/srdl2sv/components/widgets/srdl2sv_simple.yaml new file mode 100644 index 0000000..9302215 --- /dev/null +++ b/srdl2sv/components/widgets/srdl2sv_simple.yaml @@ -0,0 +1,45 @@ +# This file only contains the instantiation of the module +module_instantiation: + rtl: |- + /******************************************************************* + * CPU Interface + * ====================== + * Naming conventions + * - r2b.* -> Signals from registers to bus + * - b2r.* -> Signals from bus to registers + * - clk -> Clock that drives registers and the bus + *******************************************************************/ + assign b2r.addr = cpuif_address_i; + assign b2r.data = cpuif_data_i; + assign b2r.w_vld = cpuif_wr_vld_i; + assign b2r.r_vld = cpuif_rd_vld_i; + assign b2r.byte_en = {no_byte_enable} ? {{{bus_width_byte}{{1'b1}}}} : cpuif_byte_enable_i; + + assign cpuif_data_o = r2b.data; + assign cpuif_rdy_o = r2b.rdy; + assign cpuif_err_o = r2b.err; + signals: + - name: 'b2r' + signal_type: 'b2r_t' + - name: 'r2b' + signal_type: 'r2b_t' + input_ports: + - name: 'clk' + signal_type: '' + - name: 'cpuif_address_i' + signal_type: '[{addr_width}-1:0]' + - name: 'cpuif_wr_vld_i' + signal_type: '' + - name: 'cpuif_rd_vld_i' + signal_type: '' + - name: 'cpuif_data_i' + signal_type: '[{bus_width}-1:0]' + - name: 'cpuif_byte_enable_i' + signal_type: '[{bus_width_byte}-1:0]' + output_ports: + - name: 'cpuif_err_o' + signal_type: '' + - name: 'cpuif_rdy_o' + signal_type: '' + - name: 'cpuif_data_o' + signal_type: '[{bus_width}-1:0]' diff --git a/srdl2sv/srdl2sv.py b/srdl2sv/srdl2sv.py index 55b1947..2f7d8ca 100755 --- a/srdl2sv/srdl2sv.py +++ b/srdl2sv/srdl2sv.py @@ -72,16 +72,26 @@ def main(): print(value, file=file) # Copy over widget RTL from widget directory - widget_rtl = pkg_resources.read_text(widgets, f"srdl2sv_{config['bus']}.sv") + try: + widget_rtl = pkg_resources.read_text(widgets, f"srdl2sv_{config['bus']}.sv") - out_widget_file = f"{config['output_dir']}/srdl2sv_{config['bus']}.sv" + out_widget_file = f"{config['output_dir']}/srdl2sv_{config['bus']}.sv" - with open(out_widget_file, 'w', encoding="UTF-8") as file: - print(widget_rtl, file=file) + with open(out_widget_file, 'w', encoding="UTF-8") as file: + print(widget_rtl, file=file) - logger.info("Selected, implemented, and copied '%s' widget", config['bus']) + logger.info("Selected, implemented, and copied '%s' widget", config['bus']) + except FileNotFoundError: + # Bus might not have a corresponding SV file + logger.info("Did not find a seperate SystemVerilog file for '%s' widget", config['bus']) # Copy over generic srdl2sv_interface_pkg + if config['addrwidth_bus_spec']: + logger.info("Set address width to '%i', according to '%s' specification", + config['addrwidth'], config['bus']) + else: + logger.info("Set address width to '%i'", config['addrwidth']) + widget_if_rtl = pkg_resources.read_text(widgets, 'srdl2sv_if_pkg.sv') out_if_file = f"{config['output_dir']}/srdl2sv_if_pkg.sv"