From 28edf17a1c795c664bc9a03215cf52a399bb0138 Mon Sep 17 00:00:00 2001 From: Dennis Date: Sun, 19 Sep 2021 23:24:59 -0700 Subject: [PATCH] Pull assignment of multiplexer wires into generate for-loop --- srdl2sv/components/register.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py index 8ff47aa..b64be45 100644 --- a/srdl2sv/components/register.py +++ b/srdl2sv/components/register.py @@ -68,6 +68,9 @@ class Register(Component): # Fields will be added by get_rtl() + # Add assignment of read-wires + self.__add_sw_mux_assignments() + # Add N layers of for-loop end for i in range(self.dimensions-1, -1, -1): self.rtl_footer.append( @@ -75,10 +78,7 @@ class Register(Component): dimension = chr(97+i))) if self.dimensions and not self.generate_active: - self.rtl_footer.append("endgenerate\n") - - # Add assignment of read-wires - self.__add_sw_mux_assignments() + self.rtl_footer.append("\nendgenerate\n") # Add wire instantiation if not self.generate_active: