diff --git a/examples/aliases/log b/examples/aliases/log new file mode 100644 index 0000000..d4e852e --- /dev/null +++ b/examples/aliases/log @@ -0,0 +1,99 @@ +verilator -cc -sv srdl2sv_out/aliases.sv srdl2sv_out/srdl2sv_amba3ahblite.sv srdl2sv_out/srdl2sv_widget_if.sv +%Error: srdl2sv_out/aliases.sv:103:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_w_ack' + 103 | input example_rf__ext_main_reg__f1_ext_w_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:98:25: ... Location of original declaration + 98 | input example_rf__ext_main_reg__f1_ext_w_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:104:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_w_err' + 104 | input example_rf__ext_main_reg__f1_ext_w_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:97:25: ... Location of original declaration + 97 | input example_rf__ext_main_reg__f1_ext_w_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:109:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_r_ack' + 109 | input example_rf__ext_main_reg__f1_ext_r_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:94:25: ... Location of original declaration + 94 | input example_rf__ext_main_reg__f1_ext_r_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:110:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f1_ext_r_err' + 110 | input example_rf__ext_main_reg__f1_ext_r_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:93:25: ... Location of original declaration + 93 | input example_rf__ext_main_reg__f1_ext_r_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:118:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_w_ack' + 118 | input example_rf__ext_main_reg__f2_ext_w_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:100:25: ... Location of original declaration + 100 | input example_rf__ext_main_reg__f2_ext_w_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:119:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_w_err' + 119 | input example_rf__ext_main_reg__f2_ext_w_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:99:25: ... Location of original declaration + 99 | input example_rf__ext_main_reg__f2_ext_w_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:124:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_r_ack' + 124 | input example_rf__ext_main_reg__f2_ext_r_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:96:25: ... Location of original declaration + 96 | input example_rf__ext_main_reg__f2_ext_r_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:125:25: Duplicate declaration of signal: 'example_rf__ext_main_reg__f2_ext_r_err' + 125 | input example_rf__ext_main_reg__f2_ext_r_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:95:25: ... Location of original declaration + 95 | input example_rf__ext_main_reg__f2_ext_r_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:103:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_w_ack' + 103 | input example_rf__ext_main_reg__f1_ext_w_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:98:25: ... Location of original declaration + 98 | input example_rf__ext_main_reg__f1_ext_w_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:104:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_w_err' + 104 | input example_rf__ext_main_reg__f1_ext_w_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:97:25: ... Location of original declaration + 97 | input example_rf__ext_main_reg__f1_ext_w_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:109:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_r_ack' + 109 | input example_rf__ext_main_reg__f1_ext_r_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:94:25: ... Location of original declaration + 94 | input example_rf__ext_main_reg__f1_ext_r_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:110:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f1_ext_r_err' + 110 | input example_rf__ext_main_reg__f1_ext_r_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:93:25: ... Location of original declaration + 93 | input example_rf__ext_main_reg__f1_ext_r_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:118:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_w_ack' + 118 | input example_rf__ext_main_reg__f2_ext_w_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:100:25: ... Location of original declaration + 100 | input example_rf__ext_main_reg__f2_ext_w_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:119:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_w_err' + 119 | input example_rf__ext_main_reg__f2_ext_w_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:99:25: ... Location of original declaration + 99 | input example_rf__ext_main_reg__f2_ext_w_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:124:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_r_ack' + 124 | input example_rf__ext_main_reg__f2_ext_r_ack [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:96:25: ... Location of original declaration + 96 | input example_rf__ext_main_reg__f2_ext_r_ack[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: srdl2sv_out/aliases.sv:125:25: Duplicate declaration of port: 'example_rf__ext_main_reg__f2_ext_r_err' + 125 | input example_rf__ext_main_reg__f2_ext_r_err [4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + srdl2sv_out/aliases.sv:95:25: ... Location of original declaration + 95 | input example_rf__ext_main_reg__f2_ext_r_err[4], + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: Exiting due to 16 error(s) +make: *** [Makefile:8: verilog_compile] Error 1 diff --git a/examples/aliases/srdl2sv_out/aliases.sv b/examples/aliases/srdl2sv_out/aliases.sv index 1aa475d..98b1d3d 100644 --- a/examples/aliases/srdl2sv_out/aliases.sv +++ b/examples/aliases/srdl2sv_out/aliases.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 07 2021 11:34:07 + * - Time : November 26 2021 16:31:40 * - Path : /home/dpotter/srdl2sv/examples/aliases * - RDL file : ['aliases.rdl'] * - Hostname : ArchXPS @@ -70,61 +70,68 @@ module aliases ( - // Resets + // Reset signals declared for registers - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , - input example_rf__ext_main_reg__f1_ext_r_err [4], - input example_rf__ext_main_reg__f1_ext_r_ack [4], - input example_rf__ext_main_reg__f2_ext_r_err [4], - input example_rf__ext_main_reg__f2_ext_r_ack [4], - input example_rf__ext_main_reg__f1_ext_w_err [4], - input example_rf__ext_main_reg__f1_ext_w_ack [4], - input example_rf__ext_main_reg__f2_ext_w_err [4], - input example_rf__ext_main_reg__f2_ext_w_ack [4], - input [15:0] example_rf__ext_main_reg__f1_ext_r_data[4], - input [15:0] example_rf__ext_main_reg__f2_ext_r_data[4], - input [0:0] event1__some_event_in , - input four_field_reg__f1_hw_wr , - input [7:0] four_field_reg__f1_in , - input four_field_reg__f2_hw_wr , - input [7:0] four_field_reg__f2_in , - input four_field_reg__f3_hw_wr , - input [7:0] four_field_reg__f3_in , - input four_field_reg__f4_hw_wr , - input [7:0] four_field_reg__f4_in , + // Ports for 'General Clock' + input clk, - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output example_rf__ext_main_reg__f1_ext_w_req [4], - output [15:0] example_rf__ext_main_reg__f1_ext_w_data [4], - output [15:0] example_rf__ext_main_reg__f1_ext_w_mask [4], - output example_rf__ext_main_reg__f1_ext_r_req [4], - output example_rf__ext_alias_reg__field_1_ext_w_req[4], + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'example_rf__ext_main_reg' + input example_rf__ext_main_reg__f1_ext_r_err [4], + input example_rf__ext_main_reg__f1_ext_r_ack [4], + input example_rf__ext_main_reg__f2_ext_r_err [4], + input example_rf__ext_main_reg__f2_ext_r_ack [4], + input example_rf__ext_main_reg__f1_ext_w_err [4], + input example_rf__ext_main_reg__f1_ext_w_ack [4], + input example_rf__ext_main_reg__f2_ext_w_err [4], + input example_rf__ext_main_reg__f2_ext_w_ack [4], + output example_rf__ext_main_reg__f1_ext_w_req [4], + output [15:0] example_rf__ext_main_reg__f1_ext_w_data [4], + output [15:0] example_rf__ext_main_reg__f1_ext_w_mask [4], + input [15:0] example_rf__ext_main_reg__f1_ext_r_data [4], + output example_rf__ext_main_reg__f1_ext_r_req [4], + output example_rf__ext_alias_reg__field_1_ext_w_req [4], output [15:0] example_rf__ext_alias_reg__field_1_ext_w_data[4], output [15:0] example_rf__ext_alias_reg__field_1_ext_w_mask[4], - output example_rf__ext_alias_reg__field_1_ext_r_req[4], - output example_rf__ext_main_reg__f2_ext_w_req [4], - output [15:0] example_rf__ext_main_reg__f2_ext_w_data [4], - output [15:0] example_rf__ext_main_reg__f2_ext_w_mask [4], - output example_rf__ext_main_reg__f2_ext_r_req [4], - output event1_intr , - output [7:0] four_field_reg__f1_r , - output [7:0] four_field_reg__f2_r , - output [7:0] four_field_reg__f3_r , - output reg four_field_reg__f3_swmod , - output [7:0] four_field_reg__f4_r + output example_rf__ext_alias_reg__field_1_ext_r_req [4], + output example_rf__ext_main_reg__f2_ext_w_req [4], + output [15:0] example_rf__ext_main_reg__f2_ext_w_data [4], + output [15:0] example_rf__ext_main_reg__f2_ext_w_mask [4], + input [15:0] example_rf__ext_main_reg__f2_ext_r_data [4], + output example_rf__ext_main_reg__f2_ext_r_req [4], + + // Ports for 'event1' + output event1_intr , + input [0:0] event1__some_event_in, + + // Ports for 'four_field_reg' + input four_field_reg__f1_hw_wr, + input [7:0] four_field_reg__f1_in , + output [7:0] four_field_reg__f1_r , + input four_field_reg__f2_hw_wr, + input [7:0] four_field_reg__f2_in , + output [7:0] four_field_reg__f2_r , + input four_field_reg__f3_hw_wr, + input [7:0] four_field_reg__f3_in , + output [7:0] four_field_reg__f3_r , + output reg four_field_reg__f3_swmod, + input four_field_reg__f4_hw_wr, + input [7:0] four_field_reg__f4_in , + output [7:0] four_field_reg__f4_r + ); diff --git a/examples/counters/srdl2sv_out/counters.sv b/examples/counters/srdl2sv_out/counters.sv index 01229fd..b50d7ae 100644 --- a/examples/counters/srdl2sv_out/counters.sv +++ b/examples/counters/srdl2sv_out/counters.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 17 2021 22:15:57 + * - Time : November 26 2021 16:32:56 * - Path : /home/dpotter/srdl2sv/examples/counters * - RDL file : ['counters.rdl'] * - Hostname : ArchXPS @@ -70,36 +70,45 @@ module counters ( - // Resets + // Reset signals declared for registers input rst_async_n, - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , - input wide_counters__counter_b_lsb__cnt_incr[2], - input counter_a__cnt_hwclr , - input counter_a__cnt_incr , - input counter_a__cnt_decr , + // Ports for 'General Clock' + input clk, - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output [31:0] wide_counters__counter_b_lsb__cnt_r [2], + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'wide_counters__counter_b_lsb' + output [31:0] wide_counters__counter_b_lsb__cnt_r [2], + input wide_counters__counter_b_lsb__cnt_incr [2], output wide_counters__counter_b_lsb__cnt_overflow[2], - output [31:0] wide_counters__counter_b_msb__cnt_r [2], + + // Ports for 'wide_counters__counter_b_msb' + output [31:0] wide_counters__counter_b_msb__cnt_r [2], output wide_counters__counter_b_msb__cnt_overflow[2], - output [31:0] counter_a__cnt_r , - output counter_a__cnt_incr_thr , - output counter_a__cnt_overflow , - output counter_b_overflow_intr_intr + + // Ports for 'counter_a' + input counter_a__cnt_hwclr , + output [31:0] counter_a__cnt_r , + input counter_a__cnt_incr , + input counter_a__cnt_decr , + output counter_a__cnt_incr_thr, + output counter_a__cnt_overflow, + + // Ports for 'counter_b_overflow_intr' + output counter_b_overflow_intr_intr + ); /******************************************************************* @@ -161,36 +170,36 @@ that will fire an interrupt as soon as it wraps around. /*******************************************************************/ // Variables of register 'counter_b_lsb' -logic wide_counters__counter_b_lsb_active [2]; -logic wide_counters__counter_b_lsb_sw_wr [2]; -logic [31:0] wide_counters__counter_b_lsb_data_mux_in[2]; -logic wide_counters__counter_b_lsb_rdy_mux_in [2]; -logic wide_counters__counter_b_lsb_err_mux_in [2]; -logic [31:0] wide_counters__counter_b_lsb__cnt_q [2]; -logic wide_counters__counter_b_lsb__cnt_update_cnt[2]; -logic [31:0] wide_counters__counter_b_lsb__cnt_next [2]; -logic [0:0] wide_counters__counter_b_lsb__cnt_incr_val[2]; -logic [0:0] wide_counters__counter_b_lsb__cnt_decr_val[2]; -logic wide_counters__counter_b_lsb__cnt_decr [2]; -logic wide_counters__counter_b_lsb__cnt_incr_sat[2]; -logic wide_counters__counter_b_lsb__cnt_decr_sat[2]; +logic wide_counters__counter_b_lsb_active [2]; +logic wide_counters__counter_b_lsb_sw_wr [2]; +logic [31:0] wide_counters__counter_b_lsb_data_mux_in [2]; +logic wide_counters__counter_b_lsb_rdy_mux_in [2]; +logic wide_counters__counter_b_lsb_err_mux_in [2]; +logic [31:0] wide_counters__counter_b_lsb__cnt_q [2]; +logic wide_counters__counter_b_lsb__cnt_update_cnt [2]; +logic [31:0] wide_counters__counter_b_lsb__cnt_next [2]; +logic [0:0] wide_counters__counter_b_lsb__cnt_incr_val [2]; +logic [0:0] wide_counters__counter_b_lsb__cnt_decr_val [2]; +logic wide_counters__counter_b_lsb__cnt_decr [2]; +logic wide_counters__counter_b_lsb__cnt_incr_sat [2]; +logic wide_counters__counter_b_lsb__cnt_decr_sat [2]; logic wide_counters__counter_b_lsb__cnt_overflow_int[2]; // Variables of register 'counter_b_msb' -logic wide_counters__counter_b_msb_active [2]; -logic wide_counters__counter_b_msb_sw_wr [2]; -logic [31:0] wide_counters__counter_b_msb_data_mux_in[2]; -logic wide_counters__counter_b_msb_rdy_mux_in [2]; -logic wide_counters__counter_b_msb_err_mux_in [2]; -logic [31:0] wide_counters__counter_b_msb__cnt_q [2]; -logic wide_counters__counter_b_msb__cnt_update_cnt[2]; -logic [31:0] wide_counters__counter_b_msb__cnt_next [2]; -logic [0:0] wide_counters__counter_b_msb__cnt_incr_val[2]; -logic [0:0] wide_counters__counter_b_msb__cnt_decr_val[2]; -logic wide_counters__counter_b_msb__cnt_incr [2]; -logic wide_counters__counter_b_msb__cnt_decr [2]; -logic wide_counters__counter_b_msb__cnt_incr_sat[2]; -logic wide_counters__counter_b_msb__cnt_decr_sat[2]; +logic wide_counters__counter_b_msb_active [2]; +logic wide_counters__counter_b_msb_sw_wr [2]; +logic [31:0] wide_counters__counter_b_msb_data_mux_in [2]; +logic wide_counters__counter_b_msb_rdy_mux_in [2]; +logic wide_counters__counter_b_msb_err_mux_in [2]; +logic [31:0] wide_counters__counter_b_msb__cnt_q [2]; +logic wide_counters__counter_b_msb__cnt_update_cnt [2]; +logic [31:0] wide_counters__counter_b_msb__cnt_next [2]; +logic [0:0] wide_counters__counter_b_msb__cnt_incr_val [2]; +logic [0:0] wide_counters__counter_b_msb__cnt_decr_val [2]; +logic wide_counters__counter_b_msb__cnt_incr [2]; +logic wide_counters__counter_b_msb__cnt_decr [2]; +logic wide_counters__counter_b_msb__cnt_incr_sat [2]; +logic wide_counters__counter_b_msb__cnt_decr_sat [2]; logic wide_counters__counter_b_msb__cnt_overflow_int[2]; generate @@ -633,14 +642,14 @@ assign counter_a_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) | /******************************************************************* /*******************************************************************/ -logic counter_b_overflow_intr_active ; -logic counter_b_overflow_intr_sw_wr ; -logic [31:0] counter_b_overflow_intr_data_mux_in ; -logic counter_b_overflow_intr_rdy_mux_in ; -logic counter_b_overflow_intr_err_mux_in ; -logic [0:0] counter_b_overflow_intr__ovrflw_1_q ; +logic counter_b_overflow_intr_active ; +logic counter_b_overflow_intr_sw_wr ; +logic [31:0] counter_b_overflow_intr_data_mux_in ; +logic counter_b_overflow_intr_rdy_mux_in ; +logic counter_b_overflow_intr_err_mux_in ; +logic [0:0] counter_b_overflow_intr__ovrflw_1_q ; logic [0:0] counter_b_overflow_intr__ovrflw_1_sticky_latch; -logic [0:0] counter_b_overflow_intr__ovrflw_0_q ; +logic [0:0] counter_b_overflow_intr__ovrflw_0_q ; logic [0:0] counter_b_overflow_intr__ovrflw_0_sticky_latch; diff --git a/examples/enums/srdl2sv_out/enums.sv b/examples/enums/srdl2sv_out/enums.sv index d733e17..414e540 100644 --- a/examples/enums/srdl2sv_out/enums.sv +++ b/examples/enums/srdl2sv_out/enums.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 02 2021 23:27:37 + * - Time : November 26 2021 16:32:56 * - Path : /home/dpotter/srdl2sv/examples/enums * - RDL file : ['enums.rdl'] * - Hostname : ArchXPS @@ -35,6 +35,7 @@ * - Use Real Tabs : False * - Tab Width : 4 * - Enums Enabled : True + * - Address Errors : True * - Unpacked I/Os : True * - Register Bus Type: amba3ahblite * - Address width : 32 @@ -70,40 +71,49 @@ module enums import enums_pkg::*; import enums__regfile_1_pkg::*; ( - // Resets + // Reset signals declared for registers - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , - input enums_pkg::third_enum regfile_1__reg_c__f1_in, - input [1:0] regfile_1__reg_c__f2_in, - input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in, - input [1:0] regfile_1__reg_d__f2_in, - input enums_pkg::first_enum reg_a__f1_in , - input [1:0] reg_a__f2_in , - input enums_pkg::second_enum reg_b__f1_in , - input [1:0] reg_b__f2_in , + // Ports for 'General Clock' + input clk, + + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'regfile_1__reg_c' + input enums_pkg::third_enum regfile_1__reg_c__f1_in, + output enums_pkg::third_enum regfile_1__reg_c__f1_r , + input [1:0] regfile_1__reg_c__f2_in, + output [1:0] regfile_1__reg_c__f2_r , + + // Ports for 'regfile_1__reg_d' + input enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_in, + output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r , + input [1:0] regfile_1__reg_d__f2_in, + output [1:0] regfile_1__reg_d__f2_r , + + // Ports for 'reg_a' + input enums_pkg::first_enum reg_a__f1_in, + output enums_pkg::first_enum reg_a__f1_r , + input [1:0] reg_a__f2_in, + output [1:0] reg_a__f2_r , + + // Ports for 'reg_b' + input enums_pkg::second_enum reg_b__f1_in, + output enums_pkg::second_enum reg_b__f1_r , + input [1:0] reg_b__f2_in, + output [1:0] reg_b__f2_r - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output enums_pkg::third_enum regfile_1__reg_c__f1_r, - output [1:0] regfile_1__reg_c__f2_r, - output enums__regfile_1_pkg::fourth_enum regfile_1__reg_d__f1_r, - output [1:0] regfile_1__reg_d__f2_r, - output enums_pkg::first_enum reg_a__f1_r , - output [1:0] reg_a__f2_r , - output enums_pkg::second_enum reg_b__f1_r , - output [1:0] reg_b__f2_r ); @@ -227,9 +237,9 @@ assign regfile_1__reg_c__f2_r = regfile_1__reg_c__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign regfile_1__reg_c_data_mux_in = {{22{1'b0}}, regfile_1__reg_c__f2_q, {6{1'b0}}, regfile_1__reg_c__f1_q}; @@ -317,9 +327,9 @@ assign regfile_1__reg_d__f2_r = regfile_1__reg_d__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign regfile_1__reg_d_data_mux_in = {{22{1'b0}}, regfile_1__reg_d__f2_q, {6{1'b0}}, regfile_1__reg_d__f1_q}; @@ -407,9 +417,9 @@ assign reg_a__f2_r = reg_a__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign reg_a_data_mux_in = {{22{1'b0}}, reg_a__f2_q, {6{1'b0}}, reg_a__f1_q}; @@ -497,9 +507,9 @@ assign reg_b__f2_r = reg_b__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign reg_b_data_mux_in = {{22{1'b0}}, reg_b__f2_q, {6{1'b0}}, reg_b__f1_q}; diff --git a/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv b/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv index 6fbe473..1dee529 100644 --- a/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv +++ b/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 02 2021 23:27:37 + * - Time : November 26 2021 16:32:57 * - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles * - RDL file : ['hierarchical_regfiles.rdl'] * - Hostname : ArchXPS @@ -35,6 +35,7 @@ * - Use Real Tabs : False * - Tab Width : 4 * - Enums Enabled : True + * - Address Errors : True * - Unpacked I/Os : True * - Register Bus Type: amba3ahblite * - Address width : 32 @@ -69,49 +70,60 @@ module hierarchical_regfiles ( - // Resets + // Reset signals declared for registers - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , - input regfile_1__reg_a__f1_hw_wr , - input [15:0] regfile_1__reg_a__f1_in , - input regfile_1__reg_a__f2_hw_wr , - input [15:0] regfile_1__reg_a__f2_in , - input regfile_1__reg_b__f1_hw_wr , - input [15:0] regfile_1__reg_b__f1_in , - input regfile_1__reg_b__f2_hw_wr , - input [15:0] regfile_1__reg_b__f2_in , - input [15:0] regfile_2__regfile_3__reg_d__f1_in[3][4][2], - input [15:0] regfile_2__regfile_3__reg_d__f2_in[3][4][2], - input [7:0] regfile_2__reg_c__f1_in [3], - input [15:0] regfile_2__reg_c__f3_in [3], - input reg_e__f1_hw_wr , - input [15:0] reg_e__f1_in , - input reg_e__f2_hw_wr , - input [15:0] reg_e__f2_in , + // Ports for 'General Clock' + input clk, + + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'regfile_1__reg_a' + input regfile_1__reg_a__f1_hw_wr, + input [15:0] regfile_1__reg_a__f1_in , + output [15:0] regfile_1__reg_a__f1_r , + input regfile_1__reg_a__f2_hw_wr, + input [15:0] regfile_1__reg_a__f2_in , + output [15:0] regfile_1__reg_a__f2_r , + + // Ports for 'regfile_1__reg_b' + input regfile_1__reg_b__f1_hw_wr, + input [15:0] regfile_1__reg_b__f1_in , + output [15:0] regfile_1__reg_b__f1_r , + input regfile_1__reg_b__f2_hw_wr, + input [15:0] regfile_1__reg_b__f2_in , + output [15:0] regfile_1__reg_b__f2_r , + + // Ports for 'regfile_2__regfile_3__reg_d' + input [15:0] regfile_2__regfile_3__reg_d__f1_in[3][4][2], + output [15:0] regfile_2__regfile_3__reg_d__f1_r [3][4][2], + input [15:0] regfile_2__regfile_3__reg_d__f2_in[3][4][2], + output [15:0] regfile_2__regfile_3__reg_d__f2_r [3][4][2], + + // Ports for 'regfile_2__reg_c' + input [7:0] regfile_2__reg_c__f1_in[3], + output [7:0] regfile_2__reg_c__f2_r [3], + input [15:0] regfile_2__reg_c__f3_in[3], + + // Ports for 'reg_e' + input reg_e__f1_hw_wr, + input [15:0] reg_e__f1_in , + output [15:0] reg_e__f1_r , + input reg_e__f2_hw_wr, + input [15:0] reg_e__f2_in , + output [15:0] reg_e__f2_r - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output [15:0] regfile_1__reg_a__f1_r , - output [15:0] regfile_1__reg_a__f2_r , - output [15:0] regfile_1__reg_b__f1_r , - output [15:0] regfile_1__reg_b__f2_r , - output [15:0] regfile_2__regfile_3__reg_d__f1_r[3][4][2], - output [15:0] regfile_2__regfile_3__reg_d__f2_r[3][4][2], - output [7:0] regfile_2__reg_c__f2_r [3], - output [15:0] reg_e__f1_r , - output [15:0] reg_e__f2_r ); @@ -242,9 +254,9 @@ assign regfile_1__reg_a__f2_r = regfile_1__reg_a__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign regfile_1__reg_a_data_mux_in = {regfile_1__reg_a__f2_q, regfile_1__reg_a__f1_q}; @@ -336,9 +348,9 @@ assign regfile_1__reg_b__f2_r = regfile_1__reg_b__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign regfile_1__reg_b_data_mux_in = {regfile_1__reg_b__f2_q, regfile_1__reg_b__f1_q}; @@ -465,9 +477,9 @@ begin - /************************************** - * Assign all fields to signal to Mux * - **************************************/ + /********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign regfile_2__regfile_3__reg_d_data_mux_in[gv_a][gv_b][gv_c] = {regfile_2__regfile_3__reg_d__f2_q[gv_a][gv_b][gv_c], regfile_2__regfile_3__reg_d__f1_q[gv_a][gv_b][gv_c]}; @@ -509,6 +521,8 @@ begin // a reset, or change the sw/hw access properties assign regfile_2__reg_c__f1_q[gv_a] = regfile_2__reg_c__f1_in[gv_a]; + + //-----------------FIELD SUMMARY----------------- // name : f2 (regfile_2__reg_c[15:8]) // access : hw = r @@ -525,6 +539,8 @@ begin // Connect register to hardware output port assign regfile_2__reg_c__f2_r[gv_a] = regfile_2__reg_c__f2_q[gv_a]; + + //-----------------FIELD SUMMARY----------------- // name : f3 (regfile_2__reg_c[31:16]) // access : hw = w @@ -552,9 +568,9 @@ begin - /************************************** - * Assign all fields to signal to Mux * - **************************************/ + /********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign regfile_2__reg_c_data_mux_in[gv_a] = {regfile_2__reg_c__f3_q[gv_a], regfile_2__reg_c__f2_q[gv_a], regfile_2__reg_c__f1_q[gv_a]}; @@ -649,9 +665,9 @@ assign reg_e__f2_r = reg_e__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign reg_e_data_mux_in = {reg_e__f2_q, reg_e__f1_q}; diff --git a/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv b/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv index 14f1b35..9be794b 100644 --- a/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv +++ b/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 02 2021 23:27:21 + * - Time : November 26 2021 16:32:57 * - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy * - RDL file : ['interrupt_hierarchy.rdl'] * - Hostname : ArchXPS @@ -35,6 +35,7 @@ * - Use Real Tabs : False * - Tab Width : 4 * - Enums Enabled : True + * - Address Errors : True * - Unpacked I/Os : True * - Register Bus Type: amba3ahblite * - Address width : 32 @@ -69,53 +70,68 @@ module interrupt_hierarchy ( - // Resets + // Reset signals declared for registers input field_reset_n, - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , - input [0:0] block_a_int__crc_error_in , - input [0:0] block_a_int__len_error_in , - input [0:0] block_a_int__multi_bit_ecc_error_in, - input [3:0] block_a_int__active_ecc_master_in , - input [0:0] block_b_int__crc_error_in , - input [0:0] block_b_int__len_error_in , - input [0:0] block_b_int__multi_bit_ecc_error_in, - input [3:0] block_b_int__active_ecc_master_in , - input [0:0] block_c_int__crc_error_in , - input [0:0] block_c_int__len_error_in , - input [0:0] block_c_int__multi_bit_ecc_error_in, - input [3:0] block_c_int__active_ecc_master_in , - input [0:0] block_d_int__crc_error_in , - input [0:0] block_d_int__len_error_in , - input [0:0] block_d_int__multi_bit_ecc_error_in, - input [3:0] block_d_int__active_ecc_master_in , + // Ports for 'General Clock' + input clk, + + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'block_a_int' + output block_a_int_intr , + output block_a_int_halt , + input [0:0] block_a_int__crc_error_in , + input [0:0] block_a_int__len_error_in , + input [0:0] block_a_int__multi_bit_ecc_error_in, + input [3:0] block_a_int__active_ecc_master_in , + + // Ports for 'block_b_int' + output block_b_int_intr , + output block_b_int_halt , + input [0:0] block_b_int__crc_error_in , + input [0:0] block_b_int__len_error_in , + input [0:0] block_b_int__multi_bit_ecc_error_in, + input [3:0] block_b_int__active_ecc_master_in , + + // Ports for 'block_c_int' + output block_c_int_intr , + output block_c_int_halt , + input [0:0] block_c_int__crc_error_in , + input [0:0] block_c_int__len_error_in , + input [0:0] block_c_int__multi_bit_ecc_error_in, + input [3:0] block_c_int__active_ecc_master_in , + + // Ports for 'block_d_int' + output block_d_int_intr , + output block_d_int_halt , + input [0:0] block_d_int__crc_error_in , + input [0:0] block_d_int__len_error_in , + input [0:0] block_d_int__multi_bit_ecc_error_in, + input [3:0] block_d_int__active_ecc_master_in , + + // Ports for 'master_int' + output master_int_intr, + + // Ports for 'master_halt' + output master_halt_intr, + output master_halt_halt, + + // Ports for 'global_int' + output global_int_intr, + output global_int_halt - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output block_a_int_intr, - output block_a_int_halt, - output block_b_int_intr, - output block_b_int_halt, - output block_c_int_intr, - output block_c_int_halt, - output block_d_int_intr, - output block_d_int_halt, - output master_int_intr , - output master_halt_intr, - output master_halt_halt, - output global_int_intr , - output global_int_halt ); @@ -163,19 +179,19 @@ srdl2sv_amba3ahblite_inst /******************************************************************* /*******************************************************************/ -logic block_a_int_active ; -logic block_a_int_sw_wr ; -logic [31:0] block_a_int_data_mux_in ; -logic block_a_int_rdy_mux_in ; -logic block_a_int_err_mux_in ; -logic [0:0] block_a_int__crc_error_q ; -logic [0:0] block_a_int__crc_error_sticky_latch ; -logic [0:0] block_a_int__len_error_q ; -logic [0:0] block_a_int__len_error_sticky_latch ; -logic [0:0] block_a_int__multi_bit_ecc_error_q ; +logic block_a_int_active ; +logic block_a_int_sw_wr ; +logic [31:0] block_a_int_data_mux_in ; +logic block_a_int_rdy_mux_in ; +logic block_a_int_err_mux_in ; +logic [0:0] block_a_int__crc_error_q ; +logic [0:0] block_a_int__crc_error_sticky_latch ; +logic [0:0] block_a_int__len_error_q ; +logic [0:0] block_a_int__len_error_sticky_latch ; +logic [0:0] block_a_int__multi_bit_ecc_error_q ; logic [0:0] block_a_int__multi_bit_ecc_error_sticky_latch; -logic [3:0] block_a_int__active_ecc_master_q ; -logic [3:0] block_a_int__active_ecc_master_sticky_latch; +logic [3:0] block_a_int__active_ecc_master_q ; +logic [3:0] block_a_int__active_ecc_master_sticky_latch ; // Register-activation for 'block_a_int' @@ -346,9 +362,9 @@ assign block_a_int_intr = |(block_a_int__crc_error_q & block_a_int_en__crc_error assign block_a_int_halt = |(block_a_int__crc_error_q & ~block_a_halt_en__crc_error_q) || |(block_a_int__len_error_q & ~block_a_halt_en__len_error_q) || |(block_a_int__multi_bit_ecc_error_q & ~block_a_halt_en__multi_bit_ecc_error_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_a_int_data_mux_in = {{24{1'b0}}, block_a_int__active_ecc_master_q, {1{1'b0}}, block_a_int__multi_bit_ecc_error_q, block_a_int__len_error_q, block_a_int__crc_error_q}; @@ -461,9 +477,9 @@ end // of block_a_int_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_a_int_en_data_mux_in = {{29{1'b0}}, block_a_int_en__multi_bit_ecc_error_q, block_a_int_en__len_error_q, block_a_int_en__crc_error_q}; @@ -576,9 +592,9 @@ end // of block_a_halt_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_a_halt_en_data_mux_in = {{29{1'b0}}, block_a_halt_en__multi_bit_ecc_error_q, block_a_halt_en__len_error_q, block_a_halt_en__crc_error_q}; @@ -598,19 +614,19 @@ assign block_a_halt_en_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0]) /******************************************************************* /*******************************************************************/ -logic block_b_int_active ; -logic block_b_int_sw_wr ; -logic [31:0] block_b_int_data_mux_in ; -logic block_b_int_rdy_mux_in ; -logic block_b_int_err_mux_in ; -logic [0:0] block_b_int__crc_error_q ; -logic [0:0] block_b_int__crc_error_sticky_latch ; -logic [0:0] block_b_int__len_error_q ; -logic [0:0] block_b_int__len_error_sticky_latch ; -logic [0:0] block_b_int__multi_bit_ecc_error_q ; +logic block_b_int_active ; +logic block_b_int_sw_wr ; +logic [31:0] block_b_int_data_mux_in ; +logic block_b_int_rdy_mux_in ; +logic block_b_int_err_mux_in ; +logic [0:0] block_b_int__crc_error_q ; +logic [0:0] block_b_int__crc_error_sticky_latch ; +logic [0:0] block_b_int__len_error_q ; +logic [0:0] block_b_int__len_error_sticky_latch ; +logic [0:0] block_b_int__multi_bit_ecc_error_q ; logic [0:0] block_b_int__multi_bit_ecc_error_sticky_latch; -logic [3:0] block_b_int__active_ecc_master_q ; -logic [3:0] block_b_int__active_ecc_master_sticky_latch; +logic [3:0] block_b_int__active_ecc_master_q ; +logic [3:0] block_b_int__active_ecc_master_sticky_latch ; // Register-activation for 'block_b_int' @@ -781,9 +797,9 @@ assign block_b_int_intr = |(block_b_int__crc_error_q & block_b_int_en__crc_error assign block_b_int_halt = |(block_b_int__crc_error_q & ~block_b_halt_en__crc_error_q) || |(block_b_int__len_error_q & ~block_b_halt_en__len_error_q) || |(block_b_int__multi_bit_ecc_error_q & ~block_b_halt_en__multi_bit_ecc_error_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_b_int_data_mux_in = {{24{1'b0}}, block_b_int__active_ecc_master_q, {1{1'b0}}, block_b_int__multi_bit_ecc_error_q, block_b_int__len_error_q, block_b_int__crc_error_q}; @@ -896,9 +912,9 @@ end // of block_b_int_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_b_int_en_data_mux_in = {{29{1'b0}}, block_b_int_en__multi_bit_ecc_error_q, block_b_int_en__len_error_q, block_b_int_en__crc_error_q}; @@ -1011,9 +1027,9 @@ end // of block_b_halt_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_b_halt_en_data_mux_in = {{29{1'b0}}, block_b_halt_en__multi_bit_ecc_error_q, block_b_halt_en__len_error_q, block_b_halt_en__crc_error_q}; @@ -1033,19 +1049,19 @@ assign block_b_halt_en_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0]) /******************************************************************* /*******************************************************************/ -logic block_c_int_active ; -logic block_c_int_sw_wr ; -logic [31:0] block_c_int_data_mux_in ; -logic block_c_int_rdy_mux_in ; -logic block_c_int_err_mux_in ; -logic [0:0] block_c_int__crc_error_q ; -logic [0:0] block_c_int__crc_error_sticky_latch ; -logic [0:0] block_c_int__len_error_q ; -logic [0:0] block_c_int__len_error_sticky_latch ; -logic [0:0] block_c_int__multi_bit_ecc_error_q ; +logic block_c_int_active ; +logic block_c_int_sw_wr ; +logic [31:0] block_c_int_data_mux_in ; +logic block_c_int_rdy_mux_in ; +logic block_c_int_err_mux_in ; +logic [0:0] block_c_int__crc_error_q ; +logic [0:0] block_c_int__crc_error_sticky_latch ; +logic [0:0] block_c_int__len_error_q ; +logic [0:0] block_c_int__len_error_sticky_latch ; +logic [0:0] block_c_int__multi_bit_ecc_error_q ; logic [0:0] block_c_int__multi_bit_ecc_error_sticky_latch; -logic [3:0] block_c_int__active_ecc_master_q ; -logic [3:0] block_c_int__active_ecc_master_sticky_latch; +logic [3:0] block_c_int__active_ecc_master_q ; +logic [3:0] block_c_int__active_ecc_master_sticky_latch ; // Register-activation for 'block_c_int' @@ -1216,9 +1232,9 @@ assign block_c_int_intr = |(block_c_int__crc_error_q & block_c_int_en__crc_error assign block_c_int_halt = |(block_c_int__crc_error_q & ~block_c_halt_en__crc_error_q) || |(block_c_int__len_error_q & ~block_c_halt_en__len_error_q) || |(block_c_int__multi_bit_ecc_error_q & ~block_c_halt_en__multi_bit_ecc_error_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_c_int_data_mux_in = {{24{1'b0}}, block_c_int__active_ecc_master_q, {1{1'b0}}, block_c_int__multi_bit_ecc_error_q, block_c_int__len_error_q, block_c_int__crc_error_q}; @@ -1331,9 +1347,9 @@ end // of block_c_int_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_c_int_en_data_mux_in = {{29{1'b0}}, block_c_int_en__multi_bit_ecc_error_q, block_c_int_en__len_error_q, block_c_int_en__crc_error_q}; @@ -1446,9 +1462,9 @@ end // of block_c_halt_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_c_halt_en_data_mux_in = {{29{1'b0}}, block_c_halt_en__multi_bit_ecc_error_q, block_c_halt_en__len_error_q, block_c_halt_en__crc_error_q}; @@ -1468,19 +1484,19 @@ assign block_c_halt_en_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0]) /******************************************************************* /*******************************************************************/ -logic block_d_int_active ; -logic block_d_int_sw_wr ; -logic [31:0] block_d_int_data_mux_in ; -logic block_d_int_rdy_mux_in ; -logic block_d_int_err_mux_in ; -logic [0:0] block_d_int__crc_error_q ; -logic [0:0] block_d_int__crc_error_sticky_latch ; -logic [0:0] block_d_int__len_error_q ; -logic [0:0] block_d_int__len_error_sticky_latch ; -logic [0:0] block_d_int__multi_bit_ecc_error_q ; +logic block_d_int_active ; +logic block_d_int_sw_wr ; +logic [31:0] block_d_int_data_mux_in ; +logic block_d_int_rdy_mux_in ; +logic block_d_int_err_mux_in ; +logic [0:0] block_d_int__crc_error_q ; +logic [0:0] block_d_int__crc_error_sticky_latch ; +logic [0:0] block_d_int__len_error_q ; +logic [0:0] block_d_int__len_error_sticky_latch ; +logic [0:0] block_d_int__multi_bit_ecc_error_q ; logic [0:0] block_d_int__multi_bit_ecc_error_sticky_latch; -logic [3:0] block_d_int__active_ecc_master_q ; -logic [3:0] block_d_int__active_ecc_master_sticky_latch; +logic [3:0] block_d_int__active_ecc_master_q ; +logic [3:0] block_d_int__active_ecc_master_sticky_latch ; // Register-activation for 'block_d_int' @@ -1651,9 +1667,9 @@ assign block_d_int_intr = |(block_d_int__crc_error_q & block_d_int_en__crc_error assign block_d_int_halt = |(block_d_int__crc_error_q & ~block_d_halt_en__crc_error_q) || |(block_d_int__len_error_q & ~block_d_halt_en__len_error_q) || |(block_d_int__multi_bit_ecc_error_q & ~block_d_halt_en__multi_bit_ecc_error_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_d_int_data_mux_in = {{24{1'b0}}, block_d_int__active_ecc_master_q, {1{1'b0}}, block_d_int__multi_bit_ecc_error_q, block_d_int__len_error_q, block_d_int__crc_error_q}; @@ -1766,9 +1782,9 @@ end // of block_d_int_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_d_int_en_data_mux_in = {{29{1'b0}}, block_d_int_en__multi_bit_ecc_error_q, block_d_int_en__len_error_q, block_d_int_en__crc_error_q}; @@ -1881,9 +1897,9 @@ end // of block_d_halt_en__multi_bit_ecc_error's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign block_d_halt_en_data_mux_in = {{29{1'b0}}, block_d_halt_en__multi_bit_ecc_error_q, block_d_halt_en__len_error_q, block_d_halt_en__crc_error_q}; @@ -2022,9 +2038,9 @@ end // of master_int__module_d_int's always_ff assign master_int_intr = |(master_int__module_a_int_q & master_int_en__module_a_int_en_q) || |(master_int__module_b_int_q & master_int_en__module_b_int_en_q) || |(master_int__module_c_int_q & master_int_en__module_c_int_en_q) || |(master_int__module_d_int_q & master_int_en__module_d_int_en_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign master_int_data_mux_in = {{28{1'b0}}, master_int__module_d_int_q, master_int__module_c_int_q, master_int__module_b_int_q, master_int__module_a_int_q}; @@ -2166,9 +2182,9 @@ assign master_halt_intr = |(master_halt__module_a_int_q) || |(master_halt__modul assign master_halt_halt = |(master_halt__module_a_int_q & ~master_halt_en__module_a_halt_en_q) || |(master_halt__module_b_int_q & ~master_halt_en__module_b_halt_en_q) || |(master_halt__module_c_int_q & ~master_halt_en__module_c_halt_en_q) || |(master_halt__module_d_int_q & ~master_halt_en__module_d_halt_en_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign master_halt_data_mux_in = {{28{1'b0}}, master_halt__module_d_int_q, master_halt__module_c_int_q, master_halt__module_b_int_q, master_halt__module_a_int_q}; @@ -2308,9 +2324,9 @@ end // of master_int_en__module_d_int_en's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign master_int_en_data_mux_in = {{28{1'b0}}, master_int_en__module_d_int_en_q, master_int_en__module_c_int_en_q, master_int_en__module_b_int_en_q, master_int_en__module_a_int_en_q}; @@ -2450,9 +2466,9 @@ end // of master_halt_en__module_d_halt_en's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign master_halt_en_data_mux_in = {{28{1'b0}}, master_halt_en__module_d_halt_en_q, master_halt_en__module_c_halt_en_q, master_halt_en__module_b_halt_en_q, master_halt_en__module_a_halt_en_q}; @@ -2542,9 +2558,9 @@ assign global_int_intr = |(global_int__global_int_q & global_int_en__global_int_ assign global_int_halt = |(global_int__global_int_q) || |(global_int__global_halt_q & ~global_int_en__global_halt_en_q); -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign global_int_data_mux_in = {{30{1'b0}}, global_int__global_halt_q, global_int__global_int_q}; @@ -2630,9 +2646,9 @@ end // of global_int_en__global_halt_en's always_ff -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign global_int_en_data_mux_in = {{30{1'b0}}, global_int_en__global_halt_en_q, global_int_en__global_int_en_q}; diff --git a/examples/parameters/srdl2sv_out/paremeters.sv b/examples/parameters/srdl2sv_out/paremeters.sv index d292e10..6efb9e4 100644 --- a/examples/parameters/srdl2sv_out/paremeters.sv +++ b/examples/parameters/srdl2sv_out/paremeters.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 04 2021 23:31:13 + * - Time : November 26 2021 16:33:16 * - Path : /home/dpotter/srdl2sv/examples/parameters * - RDL file : ['parameters.rdl'] * - Hostname : ArchXPS @@ -35,6 +35,7 @@ * - Use Real Tabs : False * - Tab Width : 4 * - Enums Enabled : True + * - Address Errors : True * - Unpacked I/Os : True * - Register Bus Type: amba3ahblite * - Address width : 32 @@ -69,32 +70,41 @@ module paremeters ( - // Resets + // Reset signals declared for registers input rst_async_n, - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , - input [31:0] reg32__data_in , - input [31:0] reg32_arr__data_in[8], - input [15:0] reg16__data_in , - input [7:0] reg8__data_in , + // Ports for 'General Clock' + input clk, + + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'reg32' + input [31:0] reg32__data_in, + output [31:0] reg32__data_r , + + // Ports for 'reg32_arr' + input [31:0] reg32_arr__data_in[8], + output [31:0] reg32_arr__data_r [8], + + // Ports for 'reg16' + input [15:0] reg16__data_in, + output [15:0] reg16__data_r , + + // Ports for 'reg8' + input [7:0] reg8__data_in, + output [7:0] reg8__data_r - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output [31:0] reg32__data_r , - output [31:0] reg32_arr__data_r[8], - output [15:0] reg16__data_r , - output [7:0] reg8__data_r ); @@ -196,9 +206,9 @@ assign reg32__data_r = reg32__data_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign reg32_data_mux_in = {reg32__data_q}; @@ -272,9 +282,9 @@ begin - /************************************** - * Assign all fields to signal to Mux * - **************************************/ + /********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign reg32_arr_data_mux_in[gv_a] = {reg32_arr__data_q[gv_a]}; @@ -300,7 +310,7 @@ endgenerate logic reg16_active ; logic reg16_sw_wr ; -logic [15:0] reg16_data_mux_in; +logic [31:0] reg16_data_mux_in; logic reg16_rdy_mux_in ; logic reg16_err_mux_in ; logic [15:0] reg16__data_q ; @@ -345,11 +355,11 @@ assign reg16__data_r = reg16__data_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. -assign reg16_data_mux_in = {reg16__data_q}; +assign reg16_data_mux_in = {{16{1'b0}}, reg16__data_q}; // Internal registers are ready immediately assign reg16_rdy_mux_in = 1'b1; @@ -367,15 +377,15 @@ assign reg16_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[1:0])) || (w /******************************************************************* /*******************************************************************/ -logic reg8_active ; -logic [7:0] reg8_data_mux_in; -logic reg8_rdy_mux_in ; -logic reg8_err_mux_in ; -logic [7:0] reg8__data_q ; +logic reg8_active ; +logic [31:0] reg8_data_mux_in; +logic reg8_rdy_mux_in ; +logic reg8_err_mux_in ; +logic [7:0] reg8__data_q ; // Register-activation for 'reg8' -assign reg8_active = widget_if.addr == 38; +assign reg8_active = widget_if.addr == 40; //-----------------FIELD SUMMARY----------------- // name : data (reg8[7:0]) @@ -404,11 +414,11 @@ assign reg8__data_r = reg8__data_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. -assign reg8_data_mux_in = {reg8__data_q}; +assign reg8_data_mux_in = {{24{1'b0}}, reg8__data_q}; // Internal registers are ready immediately assign reg8_rdy_mux_in = 1'b1; diff --git a/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv b/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv index 0a0a2d0..6c96271 100644 --- a/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv +++ b/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : November 02 2021 23:27:37 + * - Time : November 26 2021 16:32:58 * - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg * - RDL file : ['simple_rw_reg.rdl'] * - Hostname : ArchXPS @@ -35,6 +35,7 @@ * - Use Real Tabs : False * - Tab Width : 4 * - Enums Enabled : True + * - Address Errors : True * - Unpacked I/Os : True * - Register Bus Type: amba3ahblite * - Address width : 32 @@ -69,42 +70,49 @@ module simple_rw_reg ( - // Resets + // Reset signals declared for registers - // Inputs - input clk , - input HRESETn , - input [31:0] HADDR , - input HWRITE , - input [2:0] HSIZE , - input [3:0] HPROT , - input [1:0] HTRANS , - input [32-1:0] HWDATA , - input HSEL , + // Ports for 'General Clock' + input clk, + + // Ports for 'AHB Protocol' + input HRESETn , + input [31:0] HADDR , + input HWRITE , + input [2:0] HSIZE , + input [3:0] HPROT , + input [1:0] HTRANS , + input [32-1:0] HWDATA , + input HSEL , + output HREADYOUT, + output HRESP , + output [32-1:0] HRDATA , + + // Ports for 'register_1d' input register_1d__f1_hw_wr, input [15:0] register_1d__f1_in , + output [15:0] register_1d__f1_r , input register_1d__f2_hw_wr, input [15:0] register_1d__f2_in , + output [15:0] register_1d__f2_r , + + // Ports for 'register_2d' input register_2d__f1_hw_wr[2], input [15:0] register_2d__f1_in [2], + output [15:0] register_2d__f1_r [2], input register_2d__f2_hw_wr[2], input [15:0] register_2d__f2_in [2], + output [15:0] register_2d__f2_r [2], + + // Ports for 'register_3d' input register_3d__f1_hw_wr[2][2], input [15:0] register_3d__f1_in [2][2], + output [15:0] register_3d__f1_r [2][2], input register_3d__f2_hw_wr[2][2], input [15:0] register_3d__f2_in [2][2], + output [15:0] register_3d__f2_r [2][2] - // Outputs - output HREADYOUT , - output HRESP , - output [32-1:0] HRDATA , - output [15:0] register_1d__f1_r, - output [15:0] register_1d__f2_r, - output [15:0] register_2d__f1_r[2], - output [15:0] register_2d__f2_r[2], - output [15:0] register_3d__f1_r[2][2], - output [15:0] register_3d__f2_r[2][2] ); @@ -227,9 +235,9 @@ assign register_1d__f2_r = register_1d__f2_q; -/************************************** - * Assign all fields to signal to Mux * - **************************************/ +/********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign register_1d_data_mux_in = {register_1d__f2_q, register_1d__f1_q}; @@ -324,9 +332,9 @@ begin - /************************************** - * Assign all fields to signal to Mux * - **************************************/ + /********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign register_2d_data_mux_in[gv_a] = {register_2d__f2_q[gv_a], register_2d__f1_q[gv_a]}; @@ -427,9 +435,9 @@ begin - /************************************** - * Assign all fields to signal to Mux * - **************************************/ + /********************************************** + * Assign all fields to signal to Mux * + **********************************************/ // Assign all fields. Fields that are not readable are tied to 0. assign register_3d_data_mux_in[gv_a][gv_b] = {register_3d__f2_q[gv_a][gv_b], register_3d__f1_q[gv_a][gv_b]};