From 3acd7516d351af52690b42dea05a7f0b118c46cd Mon Sep 17 00:00:00 2001 From: Dennis Date: Sun, 16 May 2021 12:24:52 +0200 Subject: [PATCH] Fix bug in _sw_wr/_sw_rd for non-array registers In case a register isn't instantiated as an array, the stride value the compiler returns is set to 'None'. The RTL generator should translate it to '0' (since it doesn't matter anyway). --- srdl2sv/components/register.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py index 923a950..a8bc5de 100644 --- a/srdl2sv/components/register.py +++ b/srdl2sv/components/register.py @@ -5,7 +5,6 @@ from systemrdl import RDLCompiler, RDLCompileError, RDLWalker, RDLListener, node from systemrdl.node import FieldNode # Local modules -from log.log import create_logger from components.component import Component from components.field import Field from . import templates @@ -73,7 +72,7 @@ class Register(Component): addr = self.obj.absolute_address, genvars = self.genvars_str, genvars_sum =self.genvars_sum_str, - stride = self.obj.array_stride, + stride = self.obj.array_stride if self.obj.array_stride else '0', depth = self.depth)) def __process_variables(self, obj: node.RootNode): @@ -117,5 +116,4 @@ class Register(Component): genvars_sum.append(chr(97+self.dimensions-1-i)) self.genvars_sum_str = ''.join(genvars_sum) - print(self.genvars_sum_str)