Fix wrong scope names and compilation issues with external aliases

srdl2sv/components/field.py

@@ -69,7 +69,6 @@ class Field(Component):
             self.__add_wire_const()
             self.__add_hw_rd_access()
             self.__add_swmod_swacc()
-            self.add_sw_access(obj)
         else:
             self.__add_always_ff()
 
@@ -82,7 +81,7 @@ class Field(Component):
             self.__add_swmod_swacc()
             self.__add_counter()
 
-            self.add_sw_access(obj)
+        self.add_sw_access(obj)
 
     def add_sw_access(self, obj, alias = False):
 
@@ -1113,8 +1112,8 @@ class Field(Component):
             )
 
     def create_external_rtl(self):
-        if self.properties['sw_wr']:
+        for i, alias in enumerate(self.path_underscored_vec):
-            for i, alias in enumerate(self.path_underscored_vec):
+            if self.properties['sw_wr']:
                 # Create bit-wise mask so that outside logic knows what
                 # bits it may change
                 mask = []
@@ -1132,8 +1131,10 @@ class Field(Component):
                             width = width)
                         )
 
+                wr_templ = 'external_wr_assignments' if i == 0 else 'external_wr_assignments_alias'
+
                 self.rtl_footer.append(self._process_yaml(
-                    Field.templ_dict['external_wr_assignments'],
+                    Field.templ_dict[wr_templ],
                     {'path': alias,
                      'path_wo_field': self.path_wo_field_vec[i],
                      'genvars': self.genvars_str,
@@ -1145,10 +1146,11 @@ class Field(Component):
                     }
                 ))
 
-        if self.properties['sw_rd']:
+            if self.properties['sw_rd']:
-            for i, alias in enumerate(self.path_underscored_vec):
+                rd_templ = 'external_rd_assignments' if i == 0 else 'external_rd_assignments_alias'
+
                 self.rtl_footer.append(self._process_yaml(
-                    Field.templ_dict['external_rd_assignments'],
+                    Field.templ_dict[rd_templ],
                     {'path': alias,
                      'path_wo_field': self.path_wo_field_vec[i],
                      'genvars': self.genvars_str,

srdl2sv/components/register.py

@@ -152,11 +152,12 @@ class Register(Component):
         accesswidth = self.obj.get_property('accesswidth') - 1
         self.rtl_footer.append("")
 
+        # Save name of main register
+        main_reg_name = self.name_addr_mappings[0][0]
+
         for alias_idx, na_map in enumerate(self.name_addr_mappings):
             current_bit = 0
 
-            # Start tracking errors
-
             # Handle fields
             list_of_fields = []
             bytes_read = set()
@@ -276,23 +277,25 @@ class Register(Component):
                 if self.config['external']:
                     if bytes_read:
                         for field in self.children.values():
-                            sw_err_condition_vec.append(self._process_yaml(
+                            if na_map[0] in field.readable_by:
-                                    Register.templ_dict['external_err_condition'],
+                                sw_err_condition_vec.append(self._process_yaml(
-                                    {'path': '__'.join([na_map[0], field.name]),
+                                        Register.templ_dict['external_err_condition'],
-                                     'genvars': self.genvars_str,
+                                        {'path': '__'.join([main_reg_name, field.name]),
-                                     'rd_or_wr': 'r'}
+                                         'genvars': self.genvars_str,
+                                         'rd_or_wr': 'r'}
+                                    )
                                 )
-                            )
 
                     if bytes_written:
                         for field in self.children.values():
-                            sw_err_condition_vec.append(self._process_yaml(
+                            if na_map[0] in field.writable_by:
-                                    Register.templ_dict['external_err_condition'],
+                                sw_err_condition_vec.append(self._process_yaml(
-                                    {'path': '__'.join([na_map[0], field.name]),
+                                        Register.templ_dict['external_err_condition'],
-                                     'genvars': self.genvars_str,
+                                        {'path': '__'.join([main_reg_name, field.name]),
-                                     'rd_or_wr': 'w'}
+                                         'genvars': self.genvars_str,
+                                         'rd_or_wr': 'w'}
+                                    )
                                 )
-                            )
 
                 sw_err_condition = ' || '.join(sw_err_condition_vec)
             else:
@@ -307,7 +310,7 @@ class Register(Component):
                     for field in self.children.values():
                         sw_rdy_condition_vec.append(self._process_yaml(
                                 Register.templ_dict['external_rdy_condition'],
-                                {'path': '__'.join([na_map[0], field.name]),
+                                {'path': '__'.join([main_reg_name, field.name]),
                                  'genvars': self.genvars_str,
                                  'rd_or_wr': 'r'}
                             )
@@ -327,7 +330,7 @@ class Register(Component):
                     for field in self.children.values():
                         sw_rdy_condition_vec.append(self._process_yaml(
                                 Register.templ_dict['external_rdy_condition'],
-                                {'path': '__'.join([na_map[0], field.name]),
+                                {'path': '__'.join([main_reg_name, field.name]),
                                  'genvars': self.genvars_str,
                                  'rd_or_wr': 'w'}
                             )

srdl2sv/components/templates/fields.yaml

@@ -520,6 +520,45 @@ external_wr_assignments:
           signal_type: ''
         - name: '{path}_ext_w_err'
           signal_type: ''
+external_rd_assignments_alias:
+    rtl: |-
+
+        /*********************************
+         * Alias external read interface *
+         *********************************
+         * The hardware gets notified via a different wire that 
+         * software accessed the register via an alias, but the return
+         * shall be done via the main register's I/O. This is similar to
+         * the implementation of an alias registers.
+         */
+        assign {path}_ext_r_req{genvars} = {path_wo_field}_sw_rd{genvars};
+    signals:
+        - name: '{path}_q'
+          signal_type: '{field_type}'
+    output_ports:
+        - name: '{path}_ext_r_req'
+          signal_type: 'logic'
+external_wr_assignments_alias:
+    rtl: |-
+
+        /**********************************
+         * Alias external write interface *
+         **********************************
+         * The hardware gets notified via a different wire that 
+         * software accessed the register via an alias, but the return
+         * shall be done via the main register's I/O. This is similar to
+         * the implementation of an alias registers.
+         */
+        assign {path}_ext_w_req{genvars} = {path_wo_field}_sw_wr{genvars};
+        assign {path}_ext_w_data{genvars} = widget_if.w_data[{msb_bus}:{lsb_bus}];
+        assign {path}_ext_w_mask{genvars} = {{{mask}}};
+    output_ports:
+        - name: '{path}_ext_w_req'
+          signal_type: 'logic'
+        - name: '{path}_ext_w_data'
+          signal_type: '{field_type}'
+        - name: '{path}_ext_w_mask'
+          signal_type: 'logic [{width}:0]'
 external_wr_mask_segment:
     rtl: |-
         {{{width}{{widget_if.byte_en[{idx}]}}}}