Fix generate/endgenerate and end of generate loops in regfiles

Previously, the beginning of a new loop always caused a new generate
keyword, which is wrong.

srdl2sv/components/addrmap.py

@@ -31,6 +31,9 @@ class AddrMap(Component):
         (glbl_settings['field_reset'], glbl_settings['cpuif_reset']) = \
             self.__process_global_resets()
 
+        # Use global settings to define whether a component is already in a generate block
+        glbl_settings['generate_active'] = False
+
         # Empty dictionary of register objects
         # We need a dictionary since it might be required to access the objects later
         # by name (for example, in case of aliases)

srdl2sv/components/regfile.py

@@ -42,8 +42,17 @@ class RegFile(Component):
             ]
 
         # Create generate block for register and add comment
-        if self.dimensions:
+        for i in range(self.dimensions-1, -1, -1):
+            self.rtl_footer.append(
+                RegFile.templ_dict['generate_for_end']['rtl'].format(
+                    dimension = chr(97+i)))
+
+        if self.dimensions and not glbl_settings['generate_active']:
             self.rtl_header.append("generate")
+            self.generate_initiated = True
+            glbl_settings['generate_active'] = True
+        else:
+            self.generate_initiated = False
 
         for i in range(self.dimensions):
             self.rtl_header.append(
@@ -102,6 +111,11 @@ class RegFile(Component):
 
         self.logger.info("Done generating all child-regfiles/registers")
 
+        # End generate loop
+        if self.generate_initiated:
+            glbl_settings['generate_active'] = False
+            self.rtl_footer.append("endgenerate")
+
     def __process_variables(self,
             obj: node.RegfileNode,
             parents_dimensions: list,

srdl2sv/components/register.py

@@ -38,8 +38,12 @@ class Register(Component):
             self.children.append(field_obj)
 
         # Create generate block for register and add comment
-        if self.dimensions:
+        if self.dimensions and not glbl_settings['generate_active']:
             self.rtl_header.append("generate")
+            glbl_settings['generate_active'] = True
+            self.generate_initiated = True
+        else:
+            self.generate_initiated = False
 
         for i in range(self.dimensions):
             self.rtl_header.append(
@@ -54,7 +58,8 @@ class Register(Component):
                 Register.templ_dict['generate_for_end'].format(
                     dimension = chr(97+i)))
 
-        if self.dimensions:
+        if self.generate_initiated:
+            glbl_settings['generate_active'] = False
             self.rtl_footer.append("endgenerate")
 
         # Assign variables from bus