From 5e47ff664a9d646f420d9b83dcf34a9cd88ed93e Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Mon, 18 Oct 2021 23:48:14 -0700
Subject: [PATCH] Add option to disable byte-enables

---
 srdl2sv/cli/cli.py                            | 28 +++++++++++++------
 srdl2sv/components/addrmap.py                 |  4 ++-
 .../widgets/srdl2sv_amba3ahblite.sv           | 21 ++++++++++----
 .../widgets/srdl2sv_amba3ahblite.yaml         |  3 +-
 4 files changed, 40 insertions(+), 16 deletions(-)

diff --git a/srdl2sv/cli/cli.py b/srdl2sv/cli/cli.py
index 4ac1c70..3a5e0c6 100644
--- a/srdl2sv/cli/cli.py
+++ b/srdl2sv/cli/cli.py
@@ -86,12 +86,19 @@ class CliArguments():
                   in one level of indentation. (default: %(default)s)")
 
         self.parser.add_argument(
-            "-i",
-            "--include_desc",
+            "-c",
+            "--descriptions",
             type=int,
             default=0,
-            help="Include descriptions of addrmaps (+8), regfiles (+4), registers \
-                  (+2), and fields (+1) in RTL. This is a bitfield.")
+            help="Include descriptions of addrmaps (+16), regfiles (+8), memories (+4) \
+                  registers (+2), and fields (+1) in RTL. This is a bitfield.")
+
+        self.parser.add_argument(
+            "--no_byte_enable",
+            action="store_true",
+            help="If this flag gets set, byte-enables get disabled. At that point, it \
+                  is only possible to address whole registers, not single bytes within \
+                  these registers anymore.")
 
         self.parser.add_argument(
             "IN_RDL",
@@ -158,13 +165,18 @@ class CliArguments():
         if args.bus == 'amba3ahblite':
             config['addrwidth'] = 32
 
+        # Byte enables?
+        config['no_byte_enable'] = args.no_byte_enable
+        config['list_args'].append(f"Byte enables     : {not config['no_byte_enable']}")
+
         # Set location where descirptions shall be set
         # Comparison to 1 to get a Python bool
         config['descriptions'] = {}
-        config['descriptions']['addrmap'] = (args.include_desc >> 3) & 1 == 1
-        config['descriptions']['regfile'] = (args.include_desc >> 2) & 1 == 1
-        config['descriptions']['field'] = (args.include_desc >> 1) & 1 == 1
-        config['descriptions']['register'] = (args.include_desc >> 0) & 1 == 1
+        config['descriptions']['AddrMap'] = (args.descriptions >> 4) & 1 == 1
+        config['descriptions']['RegFile'] = (args.descriptions >> 3) & 1 == 1
+        config['descriptions']['Memory'] = (args.descriptions >> 2) & 1 == 1
+        config['descriptions']['Register'] = (args.descriptions >> 1) & 1 == 1
+        config['descriptions']['Field'] = (args.descriptions >> 0) & 1 == 1
         config['list_args'].append(f"Descriptions     : {config['descriptions']}")
 
         # Set version
diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py
index 366445b..d273331 100644
--- a/srdl2sv/components/addrmap.py
+++ b/srdl2sv/components/addrmap.py
@@ -295,7 +295,9 @@ class AddrMap(Component):
 
         return self.process_yaml(
             self.widget_templ_dict['module_instantiation'],
-            {'bus_width': self.regwidth}
+            {'bus_width': self.regwidth,
+             'no_byte_enable': 1 if self.config['no_byte_enable'] else 0,
+            }
         )
 
 
diff --git a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
index acee834..1d620a5 100644
--- a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
+++ b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
@@ -27,7 +27,8 @@ module srdl2sv_amba3ahblite
     import srdl2sv_if_pkg::*;
 #(
     parameter bit FLOP_REGISTER_IF = 0,
-    parameter     BUS_BITS         = 32
+    parameter     BUS_BITS         = 32,
+    parameter     NO_BYTE_ENABLE   = 0
 )
 (
     // Outputs to internal logic
@@ -256,13 +257,21 @@ module srdl2sv_amba3ahblite
     logic                 b2r_w_vld_next;
     logic                 b2r_r_vld_next;
 
-    always_comb
+    generate
+    if (NO_BYTE_ENABLE)
     begin
-        for (int i = 0; i < BUS_BYTES; i++)
-            HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
+        assign b2r_byte_en_next = {BUS_BYTES{1'b1}}; 
+    end
+    else
+    begin
+        always_comb
+        begin
+            for (int i = 0; i < BUS_BYTES; i++)
+                HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
 
-        // Shift if not the full bus is accessed
-        b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
+            // Shift if not the full bus is accessed
+            b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
+        end
     end
 
     /***
diff --git a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml
index 1a897d8..18dfdd4 100644
--- a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml
+++ b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml
@@ -13,7 +13,8 @@ module_instantiation:
          *******************************************************************/
         srdl2sv_amba3ahblite
              #(.FLOP_REGISTER_IF (0),
-               .BUS_BITS         ({bus_width}))
+               .BUS_BITS         ({bus_width}),
+               .NO_BYTE_ENABLE   ({no_byte_enable}))
         srdl2sv_amba3ahblite_inst
              (// Outputs to internal logic
              .b2r,