From 6142a13653bf84fa6145eefd27f932a91d22e165 Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Sun, 12 Sep 2021 17:09:33 -0700
Subject: [PATCH] Add genvar-key to write-signals of external registers

---
 srdl2sv/components/templates/fields.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml
index 2892520..6d98113 100644
--- a/srdl2sv/components/templates/fields.yaml
+++ b/srdl2sv/components/templates/fields.yaml
@@ -449,10 +449,10 @@ external_wr_assignments:
         assign {path}_ext_w_req{genvars} = {path_wo_field}_sw_wr{genvars};
 
         // Assign value from bus to output
-        assign {path}_ext_w_data = b2r.data[{msb_bus}:{lsb_bus}];
+        assign {path}_ext_w_data{genvars} = b2r.data[{msb_bus}:{lsb_bus}];
 
         // Provide bit-wise mask. Only bits set to 1'b1 shall be written
-        assign {path}_ext_w_mask = {{{mask}}};
+        assign {path}_ext_w_mask{genvars} = {{{mask}}};
     output_ports:
         - name: '{path}_ext_w_req'
           signal_type: 'logic'