mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 15:08:39 +00:00
Resolve Python Lint warnings (e.g., unnecessary list comprehensions)
This commit is contained in:
parent
c7f571b909
commit
6565c33445
@ -1,10 +1,9 @@
|
|||||||
import re
|
import re
|
||||||
import importlib.resources as pkg_resources
|
import importlib.resources as pkg_resources
|
||||||
from sys import exit
|
import sys
|
||||||
import yaml
|
import yaml
|
||||||
|
|
||||||
from systemrdl import node
|
from systemrdl import node
|
||||||
from systemrdl.node import FieldNode
|
|
||||||
|
|
||||||
# Local packages
|
# Local packages
|
||||||
from components.component import Component
|
from components.component import Component
|
||||||
@ -69,7 +68,8 @@ class AddrMap(Component):
|
|||||||
|
|
||||||
self.logger.info("Done generating all child-regfiles/registers")
|
self.logger.info("Done generating all child-regfiles/registers")
|
||||||
|
|
||||||
# Create RTL of all registers
|
# Create RTL of all registers. Registers in regfiles are
|
||||||
|
# already built.
|
||||||
[x.create_rtl() for x in self.registers.values()]
|
[x.create_rtl() for x in self.registers.values()]
|
||||||
|
|
||||||
# Add bus widget ports
|
# Add bus widget ports
|
||||||
@ -82,12 +82,12 @@ class AddrMap(Component):
|
|||||||
reset_ports_rtl = [
|
reset_ports_rtl = [
|
||||||
AddrMap.templ_dict['reset_port']['rtl'].format(
|
AddrMap.templ_dict['reset_port']['rtl'].format(
|
||||||
name = name)
|
name = name)
|
||||||
for name in [x for x in self.get_resets()]
|
for name in self.get_resets()
|
||||||
]
|
]
|
||||||
|
|
||||||
# Prefetch dictionaries in local array
|
# Prefetch dictionaries in local array
|
||||||
input_dict_list = [(key, value) for (key, value) in self.get_ports('input').items()]
|
input_dict_list = self.get_ports('input').items()
|
||||||
output_dict_list = [(key, value) for (key, value) in self.get_ports('output').items()]
|
output_dict_list = self.get_ports('output').items()
|
||||||
|
|
||||||
input_signal_width = min(
|
input_signal_width = min(
|
||||||
max([len(value[0]) for (_, value) in input_dict_list]), 40)
|
max([len(value[0]) for (_, value) in input_dict_list]), 40)
|
||||||
@ -318,7 +318,7 @@ class AddrMap(Component):
|
|||||||
enum_members[var[0]],
|
enum_members[var[0]],
|
||||||
"::".join([self.name, key])))
|
"::".join([self.name, key])))
|
||||||
|
|
||||||
exit(1)
|
sys.exit(1)
|
||||||
|
|
||||||
variable_list.append(
|
variable_list.append(
|
||||||
AddrMap.templ_dict['enum_var_list_item']['rtl'].format(
|
AddrMap.templ_dict['enum_var_list_item']['rtl'].format(
|
||||||
|
Loading…
Reference in New Issue
Block a user