diff --git a/srdl2sv/components/component.py b/srdl2sv/components/component.py index bcbcf81..a0108ef 100644 --- a/srdl2sv/components/component.py +++ b/srdl2sv/components/component.py @@ -126,7 +126,12 @@ class Component(): # Define triggers for which the indentation level will increment or # decrement on the next line - trigger_re = re.compile(r'.*?((?:\bbegin\b|\{|\bcase\b)|(?:\bend\b|}|\bendcase\b))([^$]*)') + trigger_re = re.compile(r""" + .*?( + (?:\bbegin\b|\{|\bcase\b|<>)| + (?:\bend\b|}|\bendcase\b|<>) + )([^$]*) + """, flags=re.VERBOSE) rtl_indented = [] @@ -145,7 +150,7 @@ class Component(): matchObj = trigger_re.match(line_split) if matchObj: - if matchObj.group(1) in ('begin', '{', 'case'): + if matchObj.group(1) in ('begin', '{', 'case', '<>'): indent_lvl_next += 1 else: indent_lvl = indent_lvl_next - 1 @@ -159,7 +164,9 @@ class Component(): break # Add tabs - rtl_indented.append("{}{}".format(tab*indent_lvl, line)) + if line.strip() not in ('<>', '<>'): + rtl_indented.append("{}{}".format(tab*indent_lvl, line)) + return '\n'.join(rtl_indented) diff --git a/srdl2sv/components/templates/addrmap.yaml b/srdl2sv/components/templates/addrmap.yaml index 1d25554..4174852 100644 --- a/srdl2sv/components/templates/addrmap.yaml +++ b/srdl2sv/components/templates/addrmap.yaml @@ -2,8 +2,11 @@ module_declaration: rtl: |- module {name} + <> {import_package_list} + <> ( + <> // Clock & Resets input reg_clk, input bus_clk, @@ -18,6 +21,7 @@ module_declaration: // Outputs {outputs} + <> ); import_package: rtl: |-