From 695de2d330a89c6cf4606b3a2e7b3396ce6c882d Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Fri, 25 Jun 2021 11:33:57 +0200
Subject: [PATCH] Add <<INDENT>> and <<UNINDENT>> helpers to template

This allows a designer to add markers to the template to indicate where
a new level of indentation should start or end. This is apart fromt he
auto-indents caused by "case", "begin", or "{".
---
 srdl2sv/components/component.py           | 13 ++++++++++---
 srdl2sv/components/templates/addrmap.yaml |  4 ++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/srdl2sv/components/component.py b/srdl2sv/components/component.py
index bcbcf81..a0108ef 100644
--- a/srdl2sv/components/component.py
+++ b/srdl2sv/components/component.py
@@ -126,7 +126,12 @@ class Component():
 
         # Define triggers for which the indentation level will increment or
         # decrement on the next line
-        trigger_re = re.compile(r'.*?((?:\bbegin\b|\{|\bcase\b)|(?:\bend\b|}|\bendcase\b))([^$]*)')
+        trigger_re = re.compile(r"""
+            .*?(
+                (?:\bbegin\b|\{|\bcase\b|<<INDENT>>)|
+                (?:\bend\b|}|\bendcase\b|<<UNINDENT>>)
+            )([^$]*)
+            """, flags=re.VERBOSE)
 
         rtl_indented = []
 
@@ -145,7 +150,7 @@ class Component():
                 matchObj = trigger_re.match(line_split)
 
                 if matchObj:
-                    if matchObj.group(1) in ('begin', '{', 'case'):
+                    if matchObj.group(1) in ('begin', '{', 'case', '<<INDENT>>'):
                         indent_lvl_next += 1
                     else:
                         indent_lvl = indent_lvl_next - 1
@@ -159,7 +164,9 @@ class Component():
                     break
 
             # Add tabs
-            rtl_indented.append("{}{}".format(tab*indent_lvl, line))
+            if line.strip() not in ('<<INDENT>>', '<<UNINDENT>>'):
+                rtl_indented.append("{}{}".format(tab*indent_lvl, line))
+
 
 
         return '\n'.join(rtl_indented)
diff --git a/srdl2sv/components/templates/addrmap.yaml b/srdl2sv/components/templates/addrmap.yaml
index 1d25554..4174852 100644
--- a/srdl2sv/components/templates/addrmap.yaml
+++ b/srdl2sv/components/templates/addrmap.yaml
@@ -2,8 +2,11 @@
 module_declaration: 
     rtl: |-
         module {name}
+        <<INDENT>>
         {import_package_list}
+        <<UNINDENT>>
         (
+        <<INDENT>>
         // Clock & Resets
         input  reg_clk,
         input  bus_clk,
@@ -18,6 +21,7 @@ module_declaration:
 
         // Outputs
         {outputs}
+        <<UNINDENT>>
         );
 import_package:
     rtl: |-