From 6e355c62af190da6dec0940fa7a3ddd8b01a0ab2 Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Thu, 14 Oct 2021 23:16:30 -0700
Subject: [PATCH] Add support for rsvdset and rsvdsetX

---
 srdl2sv/components/addrmap.py  |  8 ++++++++
 srdl2sv/components/register.py | 11 ++++++++---
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py
index eb5d9c8..b0e8968 100644
--- a/srdl2sv/components/addrmap.py
+++ b/srdl2sv/components/addrmap.py
@@ -32,6 +32,14 @@ class AddrMap(Component):
         # Use global settings to define whether a component is already in a generate block
         glbl_settings['generate_active'] = False
 
+        # Save whether 0, 1, or x must be set for reserved bits
+        if obj.get_property('rsvdset'):
+            glbl_settings['rsvd_val'] = "1"
+        elif obj.get_property('rsvdsetX'):
+            glbl_settings['rsvd_val'] = "x"
+        else:
+            glbl_settings['rsvd_val'] = "0"
+
         # Empty dictionary of register objects
         # We need a dictionary since it might be required to access the objects later
         # by name (for example, in case of aliases)
diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py
index e79ca07..da3d182 100644
--- a/srdl2sv/components/register.py
+++ b/srdl2sv/components/register.py
@@ -157,7 +157,8 @@ class Register(Component):
                     current_bit = field.msb + 1
 
                     if empty_bits > 0:
-                        list_of_fields.append("{}'b0".format(empty_bits))
+                        list_of_fields.append(
+                            f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
 
                     list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str))
 
@@ -173,7 +174,8 @@ class Register(Component):
             no_reads = not list_of_fields
 
             if empty_bits > 0:
-                list_of_fields.append("{}'b0".format(empty_bits))
+                list_of_fields.append(
+                    f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
 
             # Create list of mux-inputs to later be picked up by carrying addrmap
             self.sw_mux_assignment_var_name.append(
@@ -482,12 +484,15 @@ class Register(Component):
         self.obj.current_idx = [0]
         self.name = obj.inst_name
 
+        # Save global settings
+        self.glbl_settings = glbl_settings
+
         # Create mapping between (alias-) name and address
         self.name_addr_mappings = [
             (self.create_underscored_path_static(obj)[3], obj.absolute_address)
             ]
 
-        # Gnerate already started?
+        # Geneate already started?
         self.generate_active = glbl_settings['generate_active']
 
         # Empty array for mux-input signals