Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-11-14 03:03:35 +00:00
Code Issues Projects Releases Wiki Activity

Add support for 'next' property to fields

Browse Source
This commit is contained in:
Dennis Potter 2021-08-15 14:10:22 -07:00
parent a74377bae7
commit 78742daba7
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 30 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
srdl2sv/components/field.py
View File

@ -740,6 +740,27 @@ class Field(Component):
write_condition == 'hw_access_no_we_wel') # Abort if no condition is set
# Actual assignment of register
if self.obj.get_property('next'):
# 'next' property is used
self.logger.debug("Found property 'next'")
assignment = self.get_signal_name(self.obj.get_property('next'))
if self.we_or_wel:
self.logger.info("This field has a 'we' or 'wel' property and "
"uses the 'next' property. Make sure this is "
"is intentional.")
else:
# No special property. Assign input to register
assignment = \
self.process_yaml(
Field.templ_dict['hw_access_field__assignment__input'],
{'path': self.path_underscored,
'genvars': self.genvars_str,
'idx': enable_mask_idx,
'field_type': self.field_type}
)
self.access_rtl['hw_write'][0].append(
self.process_yaml(
Field.templ_dict['hw_access_field'],
@ -747,6 +768,7 @@ class Field(Component):
'genvars': self.genvars_str,
'enable_mask_start': enable_mask_start_rtl,
'enable_mask_end': enable_mask_end_rtl,
'assignment': assignment,
'idx': enable_mask_idx,
'field_type': self.field_type}
)

10
srdl2sv/components/templates/fields.yaml
View File

@ -51,7 +51,7 @@ hw_access_we_wel:
if ({negl}{path}_hw_wr{genvars})
input_ports:
- name: '{path}_hw_wr'
signal_type: '{field_type}'
signal_type: 'logic'
hw_access_no_we_wel:
rtl: |-
// we or wel property not set
@ -81,7 +81,7 @@ hw_access_field:
rtl: |-
<<INDENT>>
{enable_mask_start}
{path}_q{genvars}{idx} <= {path}_in{genvars}{idx};
{path}_q{genvars}{idx} <= {assignment};
{enable_mask_end}
<<UNINDENT>>
signals:
@ -90,6 +90,12 @@ hw_access_field:
input_ports:
- name: '{path}_in'
signal_type: '{field_type}'
hw_access_field__assignment__input:
rtl: |-
{path}_in{genvars}{idx}
input_ports:
- name: '{path}_in'
signal_type: '{field_type}'
hw_access_counter:
rtl: |-
if ({path}_incr{genvars} || {path}_decr{genvars})