From 7c4f681241ca1a47e67e41d42d184e6761989644 Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Sat, 15 May 2021 18:00:22 +0200
Subject: [PATCH] Add SW read- and write wires, including assignment

---
 srdl2sv/components/register.py         | 70 +++++++++++++++++++-------
 srdl2sv/components/templates/regs.yaml |  8 +--
 2 files changed, 55 insertions(+), 23 deletions(-)

diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py
index 64b00c3..923a950 100644
--- a/srdl2sv/components/register.py
+++ b/srdl2sv/components/register.py
@@ -26,42 +26,32 @@ class Register(Component):
         self.create_logger("{}.{}".format(self.owning_addrmap, self.path), config)
         self.logger.debug('Starting to process register "{}"'.format(obj.inst_name))
 
-        if obj.is_array:
-            sel_arr = 'array'
-            array_dimensions = obj.array_dimensions
-        else:
-            sel_arr = 'single'
-            array_dimensions = [1]
-
-        depth = '[{}]'.format(']['.join(f"{i}" for i in array_dimensions))
-        dimensions = len(array_dimensions)
-
         # Create comment and provide user information about register he/she
         # is looking at.
         self.rtl_header.append(
             Register.templ_dict['reg_comment'].format(
                 name = obj.inst_name,
-                dimensions = dimensions,
-                depth = depth))
+                dimensions = self.dimensions,
+                depth = self.depth))
 
         # Create wires every register
         self.rtl_header.append(
             Register.templ_dict['rw_wire_declare'].format(
-                name = obj.inst_name,
-                depth = depth))
+                path = self.path,
+                depth = self.depth))
 
         # Create generate block for register and add comment
         self.rtl_header.append("generate")
-        for i in range(dimensions):
+        for i in range(self.dimensions):
             self.rtl_header.append(
                 Register.templ_dict['generate_for_start'].format(
                     iterator = chr(97+i),
-                    limit = array_dimensions[i]))
+                    limit = self.array_dimensions[i]))
 
         # Create RTL for fields
         # Fields should be in order in RTL,therefore, use list
         for field in obj.fields():
-            field_obj = Field(field, array_dimensions, config)
+            field_obj = Field(field, self.array_dimensions, config)
 
             if not config['disable_sanity']:
                 field_obj.sanity_checks()
@@ -69,15 +59,30 @@ class Register(Component):
             self.children.append(field_obj)
 
         # End loops
-        for i in range(dimensions-1, -1, -1):
+        for i in range(self.dimensions-1, -1, -1):
             self.rtl_footer.append(
                 Register.templ_dict['generate_for_end'].format(
                     dimension = chr(97+i)))
 
+        # Assign variables from bus
+        self.obj.current_idx = [0]
+
+        self.rtl_header.append(
+            Register.templ_dict['rw_wire_assign'].format(
+                path = self.path,
+                addr = self.obj.absolute_address,
+                genvars = self.genvars_str,
+                genvars_sum =self.genvars_sum_str,
+                stride = self.obj.array_stride,
+                depth = self.depth))
+
     def __process_variables(self, obj: node.RootNode):
         # Save object
         self.obj = obj
 
+        # Save name
+        self.name = obj.inst_name
+
         # Create full name
         self.owning_addrmap = obj.owning_addrmap.inst_name
         self.path = obj.get_path()\
@@ -86,4 +91,31 @@ class Register(Component):
 
         self.path_underscored = self.path.replace('.', '_')
 
-        self.name = obj.inst_name
+        # Determine dimensions of register
+        if obj.is_array:
+            self.sel_arr = 'array'
+            self.array_dimensions = self.obj.array_dimensions
+        else:
+            self.sel_arr = 'single'
+            self.array_dimensions = [1]
+
+        self.depth = '[{}]'.format(']['.join(f"{i}" for i in self.array_dimensions))
+        self.dimensions = len(self.array_dimensions)
+
+        # Calculate how many genvars shall be added
+        genvars = ['[{}]'.format(chr(97+i)) for i in range(self.dimensions)]
+        self.genvars_str = ''.join(genvars)
+
+        # Determine value to compare address with
+        genvars_sum = []
+        for i in range(self.dimensions):
+            if i != 0:
+                genvars_sum.append("+")
+                genvars_sum.append("*".join(map(str,self.array_dimensions[self.dimensions-i:])))
+                genvars_sum.append("*")
+
+            genvars_sum.append(chr(97+self.dimensions-1-i))
+
+        self.genvars_sum_str = ''.join(genvars_sum)
+        print(self.genvars_sum_str)
+
diff --git a/srdl2sv/components/templates/regs.yaml b/srdl2sv/components/templates/regs.yaml
index 533b099..aab8d68 100644
--- a/srdl2sv/components/templates/regs.yaml
+++ b/srdl2sv/components/templates/regs.yaml
@@ -1,10 +1,10 @@
 ---
 rw_wire_declare: |
-    logic {name}_wr {depth};
-    logic {name}_rd {depth};
+    logic {path}_sw_wr {depth};
+    logic {path}_sw_rd {depth};
 rw_wire_assign: |
-    assign {name}_bus_wr[i] = addr == {} && r_vld;
-    assign {name}_bus_wr[i] = addr == {} && r_vld;
+    assign {path}_sw_wr{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && r_vld;
+    assign {path}_sw_rd{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && w_vld;
 reg_comment: |-
     /*******************************************************************
      *******************************************************************