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Logger should always lazy evaluate variables

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This commit is contained in:
Dennis Potter 2021-10-24 12:36:17 -07:00
parent 49d1b598f0
commit 7c55cfaa8e
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
6 changed files with 66 additions and 53 deletions
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17
srdl2sv/components/addrmap.py
View File

@ -72,8 +72,7 @@ class AddrMap(Component):
obj=child,
parents_dimensions=None,
parents_strides=None,
config=config,
glbl_settings=glbl_settings)
config=config)
new_child.sanity_checks()
self.mems[child.inst_name] = new_child
elif isinstance(child, node.RegNode):
@ -100,7 +99,7 @@ class AddrMap(Component):
pass
self.logger.info(
f"Detected maximum register width of whole addrmap to be '{self.regwidth}'")
"Detected maximum register width of whole addrmap to be '%i'", self.regwidth)
# Add registers to children. This must be done in a last step
# to account for all possible alias combinations
@ -351,15 +350,19 @@ class AddrMap(Component):
enum_members[var[0]] = "::".join([self.name, key])
else:
self.logger.fatal(
f"Enum member '{var[0]}' was found at multiple locations in the same "\
"Enum member '%s' was found at multiple locations in the same "\
"main scope: \n"\
f" -- 1st occurance: '{enum_members[var[0]]}'\n"\
f" -- 2nd occurance: '{'::'.join([self.name, key])}'\n\n"\
" -- 1st occurance: '%s'\n"\
" -- 2nd occurance: '%s'\n\n"\
"This is not legal because all these enums will be defined "\
"in the same SystemVerilog scope. To share the same enum among "\
"different registers, define them on a higher level in the "\
"hierarchy.\n\n"\
"Exiting...")
"Exiting...",
var[0],
enum_members[var[0]],
'::'.join([self.name, key])
)
sys.exit(1)

36
srdl2sv/components/field.py
View File

@ -331,9 +331,9 @@ class Field(Component):
if obj_incr_value.width > self.obj.width:
self.logger.error(
f"Width of 'incr_value' signal '{obj_incr_value.get_path()}' is "
"wider than current counter field. This could potentiall cause "
"ugly errors.")
"Width of 'incr_value' signal '%s' is wider than current counter"
"field. This could potentiall cause ugly errors.",
obj_incr_value.get_path())
if obj_incr_width:
self.logger.error(
@ -399,9 +399,9 @@ class Field(Component):
if obj_decr_value.width > self.obj.width:
self.logger.error(
f"Width of 'decr_value' signal '{obj_decr_value.get_path()}' is "
"wider than current counter field. This could potentiall cause "
"ugly errors.")
"Width of 'decr_value' signal '%s' is wider than current counter"
"field. This could potentiall cause ugly errors.",
obj_decr_value.get_path())
if obj_decr_width:
self.logger.error(
@ -457,9 +457,9 @@ class Field(Component):
try:
if incr.width > 0:
self.logger.error(
f"Increment signal '{incr.inst_name}' is wider than "
"1 bit. This might result in unwanted behavior and "
"will also cause Lint-errors.")
"Increment signal '%s' is wider than 1 bit. This might"
"result in unwanted behavior and will also cause Lint-errors.",
incr.inst_name)
except AttributeError:
# 'PropRef_overflow' object has no attribute 'width'
pass
@ -498,9 +498,9 @@ class Field(Component):
try:
if decr.width > 0:
self.logger.error(
f"Decrement signal '{decr.inst_name}' is wider than "
"1 bit. This might result in unwanted behavior and "
"will also cause Lint-errors.")
"Decrement signal '%s' is wider than 1 bit. This might"
"result in unwanted behavior and will also cause Lint-errors.",
decr.decr_name)
except AttributeError:
# 'PropRef_underflow' object has no attribute 'width'
pass
@ -783,11 +783,13 @@ class Field(Component):
InterruptType.bothedge):
self.logger.info(
f"Found '{intr_type}' property for interrupt field that is "\
"Found '%s' property for interrupt field that is "\
"wider than 1-bit and has the sticky (rather than the "\
"stickybit property. In this case, the value will be "\
"latched if _any_ bit in the signal changes according to "\
"'{intr_type}'"
"'%s'",
intr_type,
intr_type
)
if intr_type != InterruptType.level:
@ -905,7 +907,7 @@ class Field(Component):
sticky, _ = self.__add_sticky(latch_signal = InterruptType.level)
if sticky:
self.logger.info(f"Found {sticky} property.")
self.logger.info("Found '%s' property.", sticky)
elif self.obj.get_property('counter'):
self.access_rtl['hw_write'] = ([
self._process_yaml(
@ -1185,7 +1187,7 @@ class Field(Component):
# kill the try block in most cases
parent_scope = enum.get_parent_scope()
self.logger.debug(f"Starting to parse '{enum}'")
self.logger.debug("Starting to parse '%s'", enum)
if isinstance(parent_scope, Reg):
enum_name = '__'.join([enum.get_scope_path().split('::')[-1], enum.__name__])
@ -1221,7 +1223,7 @@ class Field(Component):
self.field_type =\
'::'.join(['_'.join([scope, 'pkg']), enum_name])
self.logger.info(f"Parsed enum '{enum_name}'")
self.logger.info("Parsed enum '%s'", enum_name)
except AttributeError:
# In case of an AttributeError, the encode property is None. Hence,

19
srdl2sv/components/memory.py
View File

@ -101,8 +101,8 @@ class Memory(Component):
def sanity_checks(self):
if not math.log2(self.memwidth).is_integer():
self.logger.fatal( "The defined memory width must be a power of 2. "\
f"it is now defined as '{self.memwidth}'")
self.logger.fatal("The defined memory width must be a power of 2. "\
"it is now defined as '%s'", self.memwidth)
sys.exit(1)
# Determine dimensions of register
@ -112,12 +112,15 @@ class Memory(Component):
"handles this outside of the memory block.")
if self.obj.array_stride != int(self.mementries * self.memwidth / 8):
self.logger.warning(f"The memory's stride ({self.obj.array_stride}) "\
f"is unequal to the depth of the memory ({self.mementries} "\
f"* {self.memwidth} / 8 = "\
f"{int(self.mementries * self.memwidth / 8)}). This must be "\
"kept in mind when hooking up the memory interface to an "\
"external memory block.")
self.logger.warning("The memory's stride (%i) is unequal to the depth "\
"of the memory (%i * %i / 8 = %i). This must be "\
"kept in mind when hooking up the memory interface "\
"to an external memory block.",
self.obj.array_stride,
self.mementries,
self.memwidth,
int(self.mementries * self.memwidth / 8)
)
def __add_sw_mux_assignments(self):
# Create list of mux-inputs to later be picked up by carrying addrmap

20
srdl2sv/components/regfile.py
View File

@ -1,12 +1,9 @@
import importlib.resources as pkg_resources
import sys
import math
from typing import Optional
import yaml
from typing import Optional
from systemrdl import node
from systemrdl.node import FieldNode
# Local packages
from srdl2sv.components.component import Component
@ -97,7 +94,8 @@ class RegFile(Component):
self.children = {**self.regfiles, **self.registers}
# Create RTL of all registers
[x.create_rtl() for x in self.registers.values()]
for register in self.registers.values():
register.create_rtl()
self.logger.info("Done generating all child-regfiles/registers")
@ -199,15 +197,19 @@ class RegFile(Component):
enum_members[var[0]] = "::".join([self.name, key])
else:
self.logger.fatal(
f"Enum member '{var[0]}' was found at multiple locations in the same "\
"Enum member '%s' was found at multiple locations in the same "\
"main scope: \n"\
f" -- 1st occurance: '{enum_members[var[0]]}'\n"\
f" -- 2nd occurance: '{'::'.join([self.name, key])}'\n\n"\
" -- 1st occurance: '%s'\n"\
" -- 2nd occurance: '%s'\n\n"\
"This is not legal because all these enums will be defined "\
"in the same SystemVerilog scope. To share the same enum among "\
"different registers, define them on a higher level in the "\
"hierarchy.\n\n"\
"Exiting...")
"Exiting...",
var[0],
enum_members[var[0]],
'::'.join([self.name, key])
)
sys.exit(1)

15
srdl2sv/components/register.py
View File

@ -477,10 +477,13 @@ class Register(Component):
self.children[field_range].add_sw_access(field, alias=True)
except KeyError:
self.logger.fatal(
f"Range of field '{field.inst_name}' in alias register "
f"'{obj.inst_name}' does not correspond to range of field "
f"in original register '{self.name}'. This is illegal "
"according to 10.5.1 b) of the SystemRDL 2.0 LRM.")
"Range of field '%s' in alias register "
"'%s' does not correspond to range of field "
"in original register '%s'. This is illegal "
"according to 10.5.1 b) of the SystemRDL 2.0 LRM.",
field.inst_name,
obj.inst_name,
self.name)
sys.exit(1)
@ -523,8 +526,8 @@ class Register(Component):
genvars_sum.pop()
self.logger.debug(
f"Multidimensional with dimensions '{self.total_array_dimensions}' "
f"and stride '{self.total_stride}'")
"Multidimensional with dimensions '%s' and stride '%s'",
self.total_array_dimensions, self.total_stride)
except TypeError:
self.logger.debug(

6
srdl2sv/srdl2sv.py
View File

@ -41,7 +41,7 @@ def main():
except RDLCompileError:
sys.exit(1)
except FileNotFoundError:
logger.fatal(f"Could not find '{input_file}'")
logger.fatal("Could not find '%s'", input_file)
sys.exit(1)
addrmap = AddrMap(root.top, config)
@ -59,7 +59,7 @@ def main():
file=file
)
logger.info(f"Succesfully created '{out_addrmap_file}'")
logger.info("Succesfully created '%s'", out_addrmap_file)
# Start grabbing packages. This returns a dictionary for the main addrmap
# and all it's child regfiles/addrmaps
@ -79,7 +79,7 @@ def main():
with open(out_widget_file, 'w', encoding="UTF-8") as file:
print(widget_rtl, file=file)
logger.info(f"Selected, implemented, and copied '{config['bus']}' widget")
logger.info("Selected, implemented, and copied '%s' widget", config['bus'])
# Copy over generic srdl2sv_interface_pkg
widget_if_rtl = pkg_resources.read_text(widgets, 'srdl2sv_if_pkg.sv')