diff --git a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
index 47bff9f..143e2c5 100644
--- a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
+++ b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv
@@ -111,7 +111,7 @@ module srdl2sv_amba3ahblite
             begin
                 // When a transfer is extended it has the side-effecxt
                 // of extending the address phase of the next transfer
-                if (r2b.rdy)
+                if (HREADYOUT)
                 begin
                     addr_q      <= HADDR;
                     operation_q <= HWRITE ? WRITE : READ;
@@ -119,7 +119,7 @@ module srdl2sv_amba3ahblite
             end
             SEQ:
             begin
-                if (r2b.rdy)
+                if (HREADYOUT)
                 begin
                     addr_q <= addr_q; // TODO
                 end