From 85aa2f903cd3f37a6d4e6c0f8d41ec2187e6e1ff Mon Sep 17 00:00:00 2001 From: Dennis Date: Mon, 13 Sep 2021 21:52:35 -0700 Subject: [PATCH] Flops must not update when HREADYOUT == 0, not when r2b.rdy == 0 --- srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv index 47bff9f..143e2c5 100644 --- a/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv +++ b/srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv @@ -111,7 +111,7 @@ module srdl2sv_amba3ahblite begin // When a transfer is extended it has the side-effecxt // of extending the address phase of the next transfer - if (r2b.rdy) + if (HREADYOUT) begin addr_q <= HADDR; operation_q <= HWRITE ? WRITE : READ; @@ -119,7 +119,7 @@ module srdl2sv_amba3ahblite end SEQ: begin - if (r2b.rdy) + if (HREADYOUT) begin addr_q <= addr_q; // TODO end