diff --git a/srdl2sv/components/templates/register.yaml b/srdl2sv/components/templates/register.yaml
index 7394346..c04bedd 100644
--- a/srdl2sv/components/templates/register.yaml
+++ b/srdl2sv/components/templates/register.yaml
@@ -4,8 +4,8 @@ rw_wire_assign_1_dim:
 
         // Register-activation for '{path}' {alias}
         assign {path}_accss = b2r.addr == {addr};
-        assign {path}_sw_wr = {path}_accss && b2r.r_vld;
-        assign {path}_sw_rd = {path}_accss && b2r.w_vld;
+        assign {path}_sw_wr = {path}_accss && b2r.w_vld;
+        assign {path}_sw_rd = {path}_accss && b2r.r_vld;
     signals:
         - name: '{path}_sw_wr'
           signal_type: 'logic'
@@ -18,8 +18,8 @@ rw_wire_assign_multi_dim:
 
         // Register-activation for '{path}' {alias}
         assign {path}_accss{genvars} = b2r.addr == {addr}+({genvars_sum});
-        assign {path}_sw_wr{genvars} = {path}_accss{genvars} && b2r.r_vld;
-        assign {path}_sw_rd{genvars} = {path}_accss{genvars} && b2r.w_vld;
+        assign {path}_sw_wr{genvars} = {path}_accss{genvars} && b2r.w_vld;
+        assign {path}_sw_rd{genvars} = {path}_accss{genvars} && b2r.r_vld;
     signals:
         - name: '{path}_sw_wr'
           signal_type: 'logic'