From 8d86010a0a5249745de2ab84b2a7f4fcf598b576 Mon Sep 17 00:00:00 2001 From: Dennis Date: Sat, 15 May 2021 18:04:43 +0200 Subject: [PATCH] Tweak default widths of I/O ports --- srdl2sv/components/templates/addrmap.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srdl2sv/components/templates/addrmap.yaml b/srdl2sv/components/templates/addrmap.yaml index 05a773e..d2ca989 100644 --- a/srdl2sv/components/templates/addrmap.yaml +++ b/srdl2sv/components/templates/addrmap.yaml @@ -11,6 +11,6 @@ module_declaration: |- {outputs} ); input_port: |- - input {packed_dim:10s}{name:30s} {unpacked_dim}, + input {packed_dim:15s}{name:25s} {unpacked_dim}, output_port: |- - output {packed_dim:10s}{name:30s} {unpacked_dim}, + output {packed_dim:15s}{name:25s} {unpacked_dim},