mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 03:03:35 +00:00
Add counters (w/o threshold property and w/o an overflow property)
Saturating and non-saturating counters are supported. Furthermore, dynamic and static incrvalues and the incrwidth property is supported.
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GPG Key ID:
186A8AD440942BAF
@ -1,6 +1,7 @@
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import math
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import importlib.resources as pkg_resources
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import sys
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import yaml
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from systemrdl.node import FieldNode, SignalNode
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@ -47,6 +48,7 @@ class Field(Component):
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self.__add_hw_access()
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self.__add_combo()
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self.__add_swmod_swacc()
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self.__add_counter()
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self.add_sw_access(obj)
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@ -206,6 +208,240 @@ class Field(Component):
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self.access_rtl['sw_read'] = [access_rtl['sw_read']]
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self.access_rtl['sw_write'] = [access_rtl['sw_write']]
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def __add_counter(self):
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if self.obj.get_property('counter'):
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self.logger.debug("Detected counter property")
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# Determine saturation values
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if isinstance(self.obj.get_property('incrsaturate'), bool):
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if self.obj.get_property('incrsaturate'):
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incr_sat_value = 2**self.obj.width-1
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else:
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incr_sat_value = False
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else:
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incr_sat_value = self.obj.get_property('incrsaturate')
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if isinstance(self.obj.get_property('decrsaturate'), bool):
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if self.obj.get_property('decrsaturate'):
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decr_sat_value = 2**self.obj.width-1
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else:
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decr_sat_value = False
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else:
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decr_sat_value = self.obj.get_property('decrsaturate')
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# Determine with what value the counter is incremented
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# According to the spec, the incrvalue/decrvalue default to '1'
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obj_incr_value = self.obj.get_property('incrvalue')
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obj_decr_value = self.obj.get_property('decrvalue')
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obj_incr_width = self.obj.get_property('incrwidth')
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obj_decr_width = self.obj.get_property('decrwidth')
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if obj_incr_value == 0:
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incr_value = None
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incr_width = 0
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elif obj_incr_value is None:
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if obj_incr_width:
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# Decrement value is not set. Check if incrwidth is set and use
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# that is applicable
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incr_value = False
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incr_width = obj_incr_width
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# Doesn't return RTL, only adds input port
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self.process_yaml(
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Field.templ_dict['counter_incr_input'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width-1
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}
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)
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else:
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# Otherwise, use default value according to LRM
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incr_value = '1'
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incr_width = 1
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elif isinstance(obj_incr_value, int):
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incr_value = str(obj_incr_value)
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incr_width = math.floor(math.log2(obj_incr_value)+1)
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if obj_incr_width:
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self.logger.error(
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"The 'incrwidth' and 'incrvalue' properties are both "\
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"defined. This is not legal and the incrwidth property "\
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"will be ignored!")
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else:
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incr_value = self.get_signal_name(obj_incr_value)
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incr_width = obj_incr_value.width
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if obj_incr_value.width > self.obj.width:
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self.logger.error(
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"Width of 'incr_value' signal '{}' is wider than current "\
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"counter field. This could potentially cause ugly errors.".format(
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obj_incr_value.get_path()))
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if obj_incr_width:
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self.logger.error(
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"The 'incrwidth' and 'incrvalue' properties are both "\
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"defined. This is not legal and the incrwidth property "\
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"will be ignored!")
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if incr_value:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_incr_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_width': incr_width-1,
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'incr_value': incr_value,
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}
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)
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)
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if obj_decr_value == 0:
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decr_value = None
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decr_width = 0
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elif obj_decr_value is None:
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if obj_decr_width:
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# Decrement value is not set. Check if decrwidth is set and use
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# that is applicable
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decr_value = False
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decr_width = obj_decr_width
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# Doesn't return RTL, only adds input port
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self.process_yaml(
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Field.templ_dict['counter_decr_input'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr_width': decr_width-1
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}
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)
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else:
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# Otherwise, use default value according to LRM
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decr_value = '1'
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decr_width = 1
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elif isinstance(obj_decr_value, int):
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decr_value = str(obj_decr_value)
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decr_width = math.floor(math.log2(obj_decr_value)+1)
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if obj_decr_width:
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self.logger.error(
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"The 'decrwidth' and 'decrvalue' properties are both "\
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"defined. This is not legal and the decrwidth property "\
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"will be ignored!")
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else:
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decr_value = self.get_signal_name(obj_decr_value)
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decr_width = obj_decr_value.width
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if obj_decr_value.width > self.obj.width:
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self.logger.error(
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"Width of 'decr_value' signal '{}' is wider than current "\
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"counter field. This could potentially cause ugly errors.".format(
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obj_decr_value.get_path()))
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if obj_decr_width:
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self.logger.error(
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"The 'decrwidth' and 'decrvalue' properties are both "\
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"defined. This is not legal and the decrwidth property "\
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"will be ignored!")
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if decr_value:
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter_internal_decr_signal'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr_width': decr_width-1,
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'decr_value': decr_value,
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}
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)
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)
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if (incr_width or incr_value) and (decr_width or decr_value):
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sat_condition = []
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if incr_sat_value:
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sat_condition.append(
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self.process_yaml(
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Field.templ_dict['incr_decr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'greater_smaller': '>',
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'sat_value': incr_sat_value
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}
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)
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)
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if decr_sat_value:
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if sat_condition:
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sat_condition.append(' && ')
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sat_condition.append(
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self.process_yaml(
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Field.templ_dict['incr_decr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'greater_smaller': '<',
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'sat_value': decr_sat_value
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}
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)
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)
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counter_logic = self.process_yaml(
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Field.templ_dict['incr_decr_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_decr_sat_counter_condition': ''.join(sat_condition),
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}
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)
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elif incr_width or incr_value:
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sat_condition = self.process_yaml(
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Field.templ_dict['incr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'sat_value': incr_sat_value,
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}
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) if incr_sat_value else '1'
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counter_logic = self.process_yaml(
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Field.templ_dict['incr_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'incr_sat_counter_condition': sat_condition,
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}
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)
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elif decr_width or decr_value:
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sat_condition = self.process_yaml(
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Field.templ_dict['decr_sat_counter_condition'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'sat_value': decr_sat_value,
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}
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) if decr_sat_value else '1'
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counter_logic = self.process_yaml(
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Field.templ_dict['decr_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'decr_sat_counter_condition': sat_condition,
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}
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)
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else:
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self.logger.fatal("Illegal counter configuration! Both 'incr_value' "\
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"and 'decr_value' are forced to 0. If you intended "\
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"to use 'incr_width' or 'decr_width', simply don't "\
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"force 'incr_value' or 'decr_value' to any value.")
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sys.exit(1)
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self.rtl_footer.append(
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self.process_yaml(
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Field.templ_dict['counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'counter_logic': counter_logic,
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'field_type': self.field_type,
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}
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)
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)
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def __add_swmod_swacc(self):
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if self.obj.get_property('swmod'):
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self.logger.debug("Field has swmod property")
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@ -284,7 +520,17 @@ class Field(Component):
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def __add_hw_access(self):
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# Define hardware access (if applicable)
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if self.obj.get_property('hw') in (AccessType.rw, AccessType.w):
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if self.obj.get_property('counter'):
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self.access_rtl['hw_write'] = ([
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self.process_yaml(
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Field.templ_dict['hw_access_counter'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'field_type': self.field_type}
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)
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],
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False)
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elif self.obj.get_property('hw') in (AccessType.rw, AccessType.w):
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write_condition = 'hw_access_we_wel' if self.we_or_wel else 'hw_access_no_we_wel'
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# if-line of hw-access
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@ -56,6 +56,17 @@ hw_access_field:
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input_ports:
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- name: '{path}_in'
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signal_type: '{field_type}'
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hw_access_counter:
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rtl: |-
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if ({path}_update_cnt{genvars})
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begin
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{path}_q{genvars} <= {path}_next{genvars};
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end
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signals:
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- name: '{path}_update_cnt'
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signal_type: 'logic'
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- name: '{path}_next'
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signal_type: '{field_type}'
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end_field_ff:
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rtl: |-
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end // of {path}'s always_ff
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@ -181,38 +192,91 @@ swmod_assign:
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signal_type: 'logic'
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counter:
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rtl: |-
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// Combinational logic that implements counter
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always_comb
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begin
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{path}_next{genvars} = {path}_q{genvars};
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{path}_update_cnt{genvars} = 0;
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{incr_counter}
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{counter_logic}
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{decr_counter}
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end
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signals:
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- name: '{path}_update_cnt'
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signal_type: 'logic'
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- name: '{path}_next'
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signal_type: '{field_type}'
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counter_internal_incr_signal:
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rtl: |-
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assign {path}_incr_val{genvars} = {incr_value};
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signals:
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- name: '{path}_incr_val'
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signal_type: 'logic [{incr_width}:0]'
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counter_internal_decr_signal:
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rtl: |-
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assign {path}_decr_val{genvars} = {decr_value};
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signals:
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- name: '{path}_decr_val'
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signal_type: 'logic [{decr_width}:0]'
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counter_incr_input:
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rtl: ''
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input_ports:
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- name: '{path}_incr_val'
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signal_type: 'logic [{incr_width}:0]'
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counter_decr_input:
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rtl: ''
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input_ports:
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- name: '{path}_decr_val'
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signal_type: 'logic [{decr_width}:0]'
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incr_counter:
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rtl: |-
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{incr_counter_condition}
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if ({path}_incr{genvars})
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begin
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{path}_next{genvars} += {path}_{operation_str}_val{genvars};
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if ({incr_sat_counter_condition})
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begin
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{path}_next{genvars} += {path}_incr_val{genvars};
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{path}_update_cnt{genvars} = 1;
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end
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end
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input_ports:
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- name: '{path}_incr'
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signal_type: 'logic'
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decr_counter:
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rtl: |-
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{incr_counter_condition}
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if ({path}_decr{genvars})
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begin
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{path}_next{genvars} += {path}_{operation_str}_val{genvars};
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if ({decr_sat_counter_condition})
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begin
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{path}_next{genvars} -= {path}_decr_val{genvars};
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{path}_update_cnt{genvars} = 1;
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end
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incr_counter_condition:
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end
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input_ports:
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- name: '{path}_decr'
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signal_type: 'logic'
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incr_decr_counter:
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rtl: |-
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if ({path}_incr{genvars})
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if ({path}_incr{genvars} || {path}_decr{genvars})
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begin
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if ({incr_decr_sat_counter_condition})
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begin
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{path}_next{genvars} += {path}_incr_val{genvars};
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{path}_next{genvars} -= {path}_decr_val{genvars};
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{path}_update_cnt{genvars} = 1;
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end
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end
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input_ports:
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- name: '{path}_incr'
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signal_type: 'logic'
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- name: '{path}_decr'
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signal_type: 'logic'
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incr_sat_counter_condition:
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rtl: |-
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if ({path}_incr{genvars} && {path}_next{genvars} + {path}_incr_val{genvars} <= {sat_value})
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decr_counter_condition:
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rtl: |-
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if ({path}_decr{genvars})
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{path}_next{genvars} + {path}_incr_val{genvars} <= {sat_value}
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decr_sat_counter_condition:
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rtl: |-
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if ({path}_decr{genvars} && {path}_next{genvars} - {path}_decr_val{genvars} >= {sat_value})
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{path}_next{genvars} - {path}_decr_val{genvars} >= {sat_value}
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incr_decr_sat_counter_condition:
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rtl: |-
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({path}_next{genvars} + {path}_incr_val{genvars} - {path}_decr_val{genvars} {greater_smaller}= {sat_value})
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