Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 06:58:41 +00:00
Code Issues Projects Releases Wiki Activity

Add installation instructions to README.md

Browse Source
This commit is contained in:
Dennis Potter 2021-10-24 13:22:09 -07:00
parent 7c55cfaa8e
commit 9ac58367ff
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
1 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
README.md
View File

@ -15,9 +15,25 @@
# Introduction
srdl2sv is a [SystemRDL 2.0](https://www.accellera.org/images/downloads/standards/systemrdl/SystemRDL_2.0_Jan2018.pdf) to (synthesizable) [SystemVerilog](https://ieeexplore.ieee.org/document/8299595/versions) compiler. The tool is based on based on [SystemRDL/systemrdl-compiler](https://github.com/SystemRDL/systemrdl-compiler).
## Non-production ready
⚠️ Warning ⚠️ This software is still under development and not yet ready for use in production.
Warning: This software is still under development and not yet ready for use in production.
# Getting started
## Installation
A `setup.py` file is provided to install srdl2sv and all dependencies. At the time of writing this, the software was only tested on Linux but there should not be anything that prevents it from running on MacOS, Windows, or any other OS with Python >= 3.8.
To install srdl2sv globally on your Linux machine, first clone the repository:
```
git clone dennispotter.eu:Dennis/srdl2sv.git
```
enter the local repository repository
```
cd srdl2sv
```
and run
```
sudo python3 setup.py install
```
## Compiling your first RDL
The argument that is required to get started is the location of the SystemRDL file that contains the root address map. The compiler will generate a seperate SystemVerilog module for each address map it encounters in the code. Thus, if address maps are instantiated within other address maps, these will be packed into a seperate module.