diff --git a/srdl2sv/components/component.py b/srdl2sv/components/component.py
index ffe6e7e..a3517a6 100644
--- a/srdl2sv/components/component.py
+++ b/srdl2sv/components/component.py
@@ -137,8 +137,6 @@ class Component():
 
         # Go through RTL, line by line
         for line in rtl.split('\n', -1):
-            skip_incr_check = False
-
             line_split = line
 
             # This is done because the increment of the indent level must
@@ -164,7 +162,7 @@ class Component():
                     break
 
             # Add tabs
-            if line.strip() not in ('<<INDENT>>', '<<UNINDENT>>'):
+            if line.strip() not in ("<<INDENT>>", "<<UNINDENT>>", "<<SQUASH_NEWLINE>>"):
                 rtl_indented.append("{}{}".format(tab*indent_lvl, line))
 
 
diff --git a/srdl2sv/components/field.py b/srdl2sv/components/field.py
index 9519650..99e19d8 100644
--- a/srdl2sv/components/field.py
+++ b/srdl2sv/components/field.py
@@ -519,6 +519,37 @@ class Field(Component):
         self.rtl_footer = [*self.rtl_footer, swmod_props, swacc_props]
 
     def __add_hw_access(self):
+        # Mutually exclusive. systemrdl-compiler performs check for this
+        enable_mask_negl = ''
+        enable_mask = False
+
+        if self.obj.get_property('hwenable'):
+            enable_mask = self.obj.get_property('hwenable')
+        elif self.obj.get_property('hwmask'):
+            enable_mask = self.obj.get_property('hwmask')
+            enable_mask_negl = '!'
+
+        if enable_mask:
+            enable_mask_start_rtl = \
+                self.process_yaml(
+                    Field.templ_dict['hw_enable_mask_start'],
+                    {'signal': self.get_signal_name(enable_mask),
+                     'width': self.obj.width,
+                     'negl': enable_mask_negl}
+                )
+
+            enable_mask_end_rtl = \
+                self.process_yaml(
+                    Field.templ_dict['hw_enable_mask_end'],
+                    {'width': self.obj.width}
+                )
+
+            enable_mask_idx = '[idx]'
+        else:
+            enable_mask_start_rtl = '<<SQUASH_NEWLINE>>'
+            enable_mask_end_rtl = '<<SQUASH_NEWLINE>>'
+            enable_mask_idx = ''
+
         # Define hardware access (if applicable)
         if self.obj.get_property('counter'):
             self.access_rtl['hw_write'] = ([
@@ -526,7 +557,10 @@ class Field(Component):
                     Field.templ_dict['hw_access_counter'],
                     {'path': self.path_underscored,
                      'genvars': self.genvars_str,
-                     'field_type': self.field_type}
+                     'field_type': self.field_type,
+                     'enable_mask_start': enable_mask_start_rtl,
+                     'enable_mask_end': enable_mask_end_rtl,
+                     'idx': enable_mask_idx}
                 )
             ],
             False)
@@ -551,6 +585,9 @@ class Field(Component):
                     Field.templ_dict['hw_access_field'],
                     {'path': self.path_underscored,
                      'genvars': self.genvars_str,
+                     'enable_mask_start': enable_mask_start_rtl,
+                     'enable_mask_end': enable_mask_end_rtl,
+                     'idx': enable_mask_idx,
                      'field_type': self.field_type}
                 )
             )
@@ -564,7 +601,12 @@ class Field(Component):
                     Field.templ_dict['hw_access_hwset'],
                     {'path': self.path_underscored,
                      'genvars': self.genvars_str,
-                     'width': self.obj.width}
+                     'enable_mask_start': enable_mask_start_rtl,
+                     'enable_mask_end': enable_mask_end_rtl,
+                     'idx': enable_mask_idx,
+                     'constant': "{{{}{{1'b1}}}}".format(self.obj.width)
+                        if not enable_mask else "1'b1"
+                    }
                 )
             ],
             False)
@@ -574,7 +616,12 @@ class Field(Component):
                     Field.templ_dict['hw_access_hwclr'],
                     {'path': self.path_underscored,
                      'genvars': self.genvars_str,
-                     'width': self.obj.width}
+                     'enable_mask_start': enable_mask_start_rtl,
+                     'enable_mask_end': enable_mask_end_rtl,
+                     'idx': enable_mask_idx,
+                     'constant': "{{{}{{1'b0}}}}".format(self.obj.width)
+                        if not enable_mask else "1'b0"
+                    }
                 )
             ],
             False)
@@ -640,6 +687,7 @@ class Field(Component):
                     continue
 
                 order_list_rtl = [*order_list_rtl, *unpacked_access_rtl[0]]
+
                 order_list_rtl.append("else")
 
                 # If the access_rtl entry has an abortion entry, do not print
diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml
index 5c006e7..4d5d651 100644
--- a/srdl2sv/components/templates/fields.yaml
+++ b/srdl2sv/components/templates/fields.yaml
@@ -30,12 +30,22 @@ sw_access_field_swwel:
 sw_access_byte: 
     rtl: |-
         if (byte_enable[{i}])
-        begin
+        <<INDENT>>
         {path}_q{genvars}[{msb_field}:{lsb_field}] <= sw_wr_bus[{msb_bus}:{lsb_bus}];
-        end
+        <<UNINDENT>>
     signals:
         - name: '{path}_q'
           signal_type: '{field_type}'
+hw_enable_mask_start: 
+    rtl: |-
+        for (int idx = 0; idx < {width}; idx++)
+        begin
+        if ({negl}{signal}[idx])
+        <<INDENT>>
+hw_enable_mask_end: 
+    rtl: |-
+        <<UNINDENT>>
+        end // for (int idx = 0; idx < {width}; idx++)
 hw_access_we_wel: 
     rtl: |-
         if ({negl}{path}_hw_wr{genvars})
@@ -48,26 +58,32 @@ hw_access_no_we_wel:
 hw_access_hwset:
     rtl: |-
         if ({path}_hwset{genvars})
-        begin
-          {path}_q{genvars} <= {{{width}{{1'b1}}}};
-        end
+        <<INDENT>>
+        {enable_mask_start}
+        {path}_q{genvars}{idx} <= {constant};
+        {enable_mask_end}
+        <<UNINDENT>>
     input_ports:
         - name: '{path}_hwset'
           signal_type: 'logic'
 hw_access_hwclr:
     rtl: |-
         if ({path}_hwclr{genvars})
-        begin
-          {path}_q{genvars} <= {{{width}{{1'b0}}}};
-        end
+        <<INDENT>>
+        {enable_mask_start}
+        {path}_q{genvars}{idx} <= {constant};
+        {enable_mask_end}
+        <<UNINDENT>>
     input_ports:
         - name: '{path}_hwclr'
           signal_type: 'logic'
 hw_access_field: 
     rtl: |-
-        begin
-        {path}_q{genvars} <= {path}_in{genvars};
-        end
+        <<INDENT>>
+        {enable_mask_start}
+        {path}_q{genvars}{idx} <= {path}_in{genvars}{idx};
+        {enable_mask_end}
+        <<UNINDENT>>
     signals:
         - name: '{path}_q'
           signal_type: '{field_type}'
@@ -77,9 +93,11 @@ hw_access_field:
 hw_access_counter:
     rtl: |-
         if ({path}_update_cnt{genvars})
-        begin
-        {path}_q{genvars} <= {path}_next{genvars};
-        end
+        <<INDENT>>
+        {enable_mask_start}
+        {path}_q{genvars}{idx} <= {path}_next{genvars}{idx};
+        {enable_mask_end}
+        <<UNINDENT>>
     signals:
         - name: '{path}_update_cnt'
           signal_type: 'logic'