mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Minor clean up, mostly Python Lint warnings
This commit is contained in:
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1ed801a565
commit
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GPG Key ID:
186A8AD440942BAF
@ -20,7 +20,7 @@
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*
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* Generation information:
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* - User: : dpotter
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* - Time : October 20 2021 22:32:15
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* - Time : October 20 2021 23:49:07
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* - Path : /home/dpotter/srdl2sv_second_repo/examples/simple_rw_reg
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* - RDL file : ['simple_rw_reg.rdl']
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* - Hostname : ArchXPS
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@ -30,7 +30,7 @@
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*
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* Commandline arguments to srdl2sv:
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* - Ouput Directory : ./srdl2sv_out
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* - Stream Log Level : WARNING
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* - Stream Log Level : INFO
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* - File Log Level : INFO
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* - Use Real Tabs : False
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* - Tab Width : 4
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@ -175,7 +175,7 @@ assign register_1d_sw_wr = register_1d_active && b2r.w_vld;
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : {'we', 'sw'}
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// flags : ['sw', 'we']
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// external : False
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//-----------------------------------------------
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@ -203,7 +203,7 @@ assign register_1d__f1_r = register_1d__f1_q;
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : {'we', 'sw'}
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// flags : ['sw', 'we']
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// external : False
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//-----------------------------------------------
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@ -270,7 +270,7 @@ begin
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : {'we', 'sw'}
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// flags : ['sw', 'we']
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// external : False
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//-----------------------------------------------
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@ -298,7 +298,7 @@ begin
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : {'we', 'sw'}
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// flags : ['sw', 'we']
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// external : False
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//-----------------------------------------------
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@ -371,7 +371,7 @@ begin
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : {'we', 'sw'}
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// flags : ['sw', 'we']
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// external : False
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//-----------------------------------------------
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@ -399,7 +399,7 @@ begin
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// access : hw = rw
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// sw = rw (precedence)
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// reset : - / -
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// flags : {'we', 'sw'}
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// flags : ['sw', 'we']
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// external : False
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//-----------------------------------------------
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@ -14,6 +14,7 @@ logging_map = {
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}
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class CliArguments():
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# TODO: Add option to remove timestamp (for SCM)
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def __init__(self):
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self.parser = argparse.ArgumentParser(
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@ -1,6 +1,9 @@
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import re
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import importlib.resources as pkg_resources
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import sys
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import getpass
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import socket
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import time
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import os
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import yaml
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from systemrdl import node
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@ -24,7 +27,7 @@ class AddrMap(Component):
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super().__init__(obj, config)
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# Check if global resets are defined
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glbl_settings = dict()
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glbl_settings = {}
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# Set defaults so that some of the common component methods work
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self.total_dimensions = 0
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@ -44,9 +47,9 @@ class AddrMap(Component):
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# Empty dictionary of register objects
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# We need a dictionary since it might be required to access the objects later
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# by name (for example, in case of aliases)
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self.registers = dict()
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self.regfiles = dict()
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self.mems = dict()
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self.registers = {}
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self.regfiles = {}
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self.mems = {}
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self.regwidth = 0
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# Traverse through children
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@ -80,8 +83,8 @@ class AddrMap(Component):
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# Simply ignore nodes like SignalNodes
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pass
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self.logger.info("Detected maximum register width of whole addrmap to be '{}'".format(
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self.regwidth))
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self.logger.info(
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f"Detected maximum register width of whole addrmap to be '{self.regwidth}'")
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# Add registers to children. This must be done in a last step
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# to account for all possible alias combinations
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@ -91,7 +94,8 @@ class AddrMap(Component):
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# Create RTL of all registers. Registers in regfiles are
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# already built and so are memories.
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[x.create_rtl() for x in self.registers.values()]
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for register in self.registers.values():
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register.create_rtl()
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# Add bus widget ports
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widget_rtl = self.__get_widget_ports_rtl()
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@ -176,11 +180,6 @@ class AddrMap(Component):
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import_package_list.pop()
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import getpass
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import socket
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import time
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import os
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self.rtl_header.append(
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AddrMap.templ_dict['header'].format(
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user = getpass.getuser(),
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@ -251,7 +250,7 @@ class AddrMap(Component):
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)
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def __add_signal_instantiation(self):
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dict_list = [(key, value) for (key, value) in self.get_signals(True).items()]
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dict_list = list(self.get_signals(True).items())
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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name_width = min(max([len(key) for (key, _) in dict_list]), 40)
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@ -274,7 +273,7 @@ class AddrMap(Component):
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def __get_widget_ports_rtl(self):
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self.widget_templ_dict = yaml.load(
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pkg_resources.read_text(widgets, 'srdl2sv_{}.yaml'.format(self.config['bus'])),
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pkg_resources.read_text(widgets, f"srdl2sv_{self.config['bus']}.yaml"),
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Loader=yaml.FullLoader)
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return self.process_yaml(
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@ -301,27 +300,28 @@ class AddrMap(Component):
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def get_package_names(self) -> set():
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names = set()
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for i in self.registers.values():
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for x in i.get_typedefs().values():
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names.add(x.scope)
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for register in self.registers.values():
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for typedef in register.get_typedefs().values():
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names.add(typedef.scope)
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[names.update(x.get_package_names()) for x in self.regfiles.values()]
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for regfile in self.regfiles.values():
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names.update(regfile.get_package_names())
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return names
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def get_package_rtl(self, tab_width: int = 4, real_tabs = False) -> dict():
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if not self.config['enums']:
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return dict()
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return {}
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# First go through all registers in this scope to generate a package
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package_rtl = []
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rtl_return = dict()
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rtl_return = {}
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# Need to keep track of enum names since they shall be unique
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# per scope
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enum_rtl = dict()
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enum_rtl = {}
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enum_rtl[self.name] = []
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enum_members = dict()
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enum_members = {}
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for i in self.registers.values():
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for key, value in i.get_typedefs().items():
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@ -335,18 +335,15 @@ class AddrMap(Component):
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enum_members[var[0]] = "::".join([self.name, key])
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else:
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self.logger.fatal(
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"Enum member '{}' was found at multiple locations in the same "\
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f"Enum member '{var[0]}' was found at multiple locations in the same "\
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"main scope: \n"\
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" -- 1st occurance: '{}'\n"\
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" -- 2nd occurance: '{}'\n\n"\
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f" -- 1st occurance: '{enum_members[var[0]]}'\n"\
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f" -- 2nd occurance: '{'::'.join([self.name, key])}'\n\n"\
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"This is not legal because all these enums will be defined "\
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"in the same SystemVerilog scope. To share the same enum among "\
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"different registers, define them on a higher level in the "\
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"hierarchy.\n\n"\
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"Exiting...".format(
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var[0],
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enum_members[var[0]],
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"::".join([self.name, key])))
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"Exiting...")
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sys.exit(1)
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@ -1,10 +1,10 @@
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import re
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import sys
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from itertools import chain
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from typing import NamedTuple
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from systemrdl import node
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from dataclasses import dataclass
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from systemrdl import node
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# Local modules
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from log.log import create_logger
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@ -30,13 +30,13 @@ class Component():
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def __init__(self, obj, config):
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self.rtl_header = []
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self.rtl_footer = []
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self.children = dict()
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self.typedefs = dict()
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self.ports = dict()
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self.children = {}
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self.typedefs = {}
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self.ports = {}
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self.resets = set()
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self.signals = dict()
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self.ports['input'] = dict()
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self.ports['output'] = dict()
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self.signals = {}
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self.ports['input'] = {}
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self.ports['output'] = {}
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self.field_type = ''
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# Save object
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@ -65,14 +65,12 @@ class Component():
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}
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# Create logger object
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self.create_logger("{}".format(self.full_path), config)
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self.logger.debug('Starting to process {} "{}"'.format(
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self.__class__.__name__,
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obj.inst_name))
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self.create_logger(self.full_path, config)
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self.logger.debug(f"Starting to process {self.__class__.__name__} '{obj.inst_name}'")
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def create_logger(self, name: str, config: dict):
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self.logger = create_logger(
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"{}".format(name),
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name,
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stream_log_level=config['stream_log_level'],
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file_log_level=config['file_log_level'],
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file_name=config['file_log_location'])
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@ -81,23 +79,23 @@ class Component():
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def get_resets(self):
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self.logger.debug("Return reset list")
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for x in self.children.values():
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self.resets |= x.get_resets()
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for child in self.children.values():
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self.resets |= child.get_resets()
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return self.resets
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def get_ports(self, port_type: str):
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self.logger.debug("Return port list")
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for x in self.children.values():
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self.ports[port_type] |= x.get_ports(port_type)
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for child in self.children.values():
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self.ports[port_type] |= child.get_ports(port_type)
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return self.ports[port_type]
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def get_max_dim_depth(self) -> int:
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self.logger.debug("Return depth '{}' for dimensions (including "\
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"parents) '{}'".format(self.total_dimensions,
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self.total_array_dimensions))
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self.logger.debug(f"Return depth '{self.total_dimensions}' for dimensions (including "\
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f"parents) '{self.total_array_dimensions}'")
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return max([
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self.total_dimensions,
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*[x.get_max_dim_depth() for x in self.children.values()]
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@ -107,16 +105,16 @@ class Component():
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self.logger.debug("Return signal list")
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if not no_children:
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for x in self.children.values():
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self.signals |= x.get_signals()
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for child in self.children.values():
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self.signals |= child.get_signals()
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return self.signals
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def get_typedefs(self):
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self.logger.debug("Return typedef list")
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for x in self.children.values():
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self.typedefs |= x.get_typedefs()
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for child in self.children.values():
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self.typedefs |= child.get_typedefs()
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return self.typedefs
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@ -126,8 +124,8 @@ class Component():
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# Loop through children and append RTL
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rtl_children = []
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for x in self.children.values():
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rtl_children.append(x.get_rtl())
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for child in self.children.values():
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rtl_children.append(child.get_rtl())
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# Concatenate header, main, and footer
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rtl = [*self.rtl_header, *rtl_children, *self.rtl_footer]
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@ -153,10 +151,10 @@ class Component():
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# Define triggers for which the indentation level will increment or
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# decrement on the next line
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trigger_re = re.compile(r"""
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.*?(
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.*?(?P<keyword>
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(?:\bbegin\b|\{|\bcase\b|<<INDENT>>)|
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(?:\bend\b|}|\bendcase\b|<<UNINDENT>>)
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)([^$]*)
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)(?P<remainder>[^$]*)
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""", flags=re.VERBOSE)
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rtl_indented = []
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@ -171,16 +169,14 @@ class Component():
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while 1:
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# Check if indentation must be decremented
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matchObj = trigger_re.match(line_split)
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if matchObj:
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if matchObj.group(1) in ('begin', '{', 'case', '<<INDENT>>'):
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if match_obj := trigger_re.match(line_split):
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if match_obj.group('keyword') in ('begin', '{', 'case', '<<INDENT>>'):
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indent_lvl_next += 1
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else:
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indent_lvl = indent_lvl_next - 1
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indent_lvl_next -= 1
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line_split = matchObj.group(2)
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line_split = match_obj.group('remainder')
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if not line_split:
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break
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@ -189,9 +185,7 @@ class Component():
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# Add tabs
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if line.strip() not in ("<<INDENT>>", "<<UNINDENT>>", "<<SQUASH_NEWLINE>>"):
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rtl_indented.append("{}{}".format(tab*indent_lvl, line))
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rtl_indented.append(f"{tab*indent_lvl}{line}")
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return '\n'.join(rtl_indented)
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@ -199,12 +193,12 @@ class Component():
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def get_underscored_path(path: str, owning_addrmap: str):
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return path\
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.replace('[]', '')\
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.replace('{}.'.format(owning_addrmap), '')\
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.replace(f"{owning_addrmap}.", '')\
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.replace('.', '__')
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@staticmethod
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def split_dimensions(path: str):
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re_dimensions = re.compile('(\[[^]]*\])')
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re_dimensions = re.compile(r'(\[[^]]*\])')
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new_path = re_dimensions.sub('', path)
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return (new_path, ''.join(re_dimensions.findall(path)))
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@ -229,19 +223,19 @@ class Component():
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elif isinstance(obj, node.SignalNode):
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# Must add it to signal list
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self.ports['input'][obj.inst_name] =\
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("logic" if obj.width == 1 else 'logic [{}:0]'.format(obj.width), [])
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("logic" if obj.width == 1 else f"logic [{obj.width}:0]", [])
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else:
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name.append('_')
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name.append(obj.name)
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# This is a property. Check if the original field actually has this property
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if obj.name == "intr" or obj.name == "halt":
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if obj.name in ("intr", "halt"):
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pass
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elif not obj.node.get_property(obj.name):
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self.logger.fatal("Reference to the property '{}' of instance '{}' found. "
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"This instance does hold the reference property! Please "
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"fix this if you want me to do my job properly."
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.format(obj.name, obj.node.get_path()))
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self.logger.fatal(f"Reference to the property '{obj.name}' of instance "
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f"'{obj.node.get_path()}' found. This instance does "
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"hold the reference property! Please fix this if you "
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"want me to do my job properly.")
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sys.exit(1)
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@ -259,14 +253,14 @@ class Component():
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if skip_signals:
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raise KeyError
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for x in yaml_obj['signals']:
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for signal in yaml_obj['signals']:
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try:
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array_dimensions = [] if x['no_unpacked'] else self.total_array_dimensions
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array_dimensions = [] if signal['no_unpacked'] else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.signals[x['name'].format(**values)] =\
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(x['signal_type'].format(**values),
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self.signals[signal['name'].format(**values)] =\
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(signal['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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@ -275,14 +269,14 @@ class Component():
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if skip_inputs:
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raise KeyError
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for x in yaml_obj['input_ports']:
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for input in yaml_obj['input_ports']:
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try:
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array_dimensions = [] if x['no_unpacked'] else self.total_array_dimensions
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array_dimensions = [] if input['no_unpacked'] else self.total_array_dimensions
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except KeyError:
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array_dimensions = self.total_array_dimensions
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self.ports['input'][x['name'].format(**values)] =\
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(x['signal_type'].format(**values),
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self.ports['input'][input['name'].format(**values)] =\
|
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(input['signal_type'].format(**values),
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array_dimensions)
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except (TypeError, KeyError):
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pass
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@ -291,14 +285,14 @@ class Component():
|
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if skip_outputs:
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raise KeyError
|
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|
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for x in yaml_obj['output_ports']:
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for output in yaml_obj['output_ports']:
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try:
|
||||
array_dimensions = [] if x['no_unpacked'] else self.total_array_dimensions
|
||||
array_dimensions = [] if output['no_unpacked'] else self.total_array_dimensions
|
||||
except KeyError:
|
||||
array_dimensions = self.total_array_dimensions
|
||||
|
||||
self.ports['output'][x['name'].format(**values)] =\
|
||||
(x['signal_type'].format(**values),
|
||||
self.ports['output'][output['name'].format(**values)] =\
|
||||
(output['signal_type'].format(**values),
|
||||
array_dimensions)
|
||||
except (TypeError, KeyError):
|
||||
pass
|
||||
@ -308,7 +302,7 @@ class Component():
|
||||
|
||||
@staticmethod
|
||||
def process_reset_signal(reset_signal):
|
||||
rst = dict()
|
||||
rst = {}
|
||||
|
||||
try:
|
||||
rst['name'] = reset_signal.inst_name
|
||||
@ -340,8 +334,7 @@ class Component():
|
||||
def create_underscored_path_static(obj):
|
||||
owning_addrmap = obj.owning_addrmap.inst_name
|
||||
full_path = Component.split_dimensions(obj.get_path())[0]
|
||||
path = full_path\
|
||||
.replace('{}.'.format(owning_addrmap), '')
|
||||
path = full_path.replace(f"{owning_addrmap}.", '')
|
||||
|
||||
path_underscored = path.replace('.', '__')
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@ import sys
|
||||
import yaml
|
||||
|
||||
from systemrdl.node import FieldNode, SignalNode
|
||||
from systemrdl.component import Reg, Regfile, Addrmap, Root
|
||||
from systemrdl.component import Reg, Regfile
|
||||
from systemrdl.rdltypes import PrecedenceType, AccessType, OnReadType, OnWriteType, InterruptType
|
||||
|
||||
# Local modules
|
||||
@ -61,7 +61,7 @@ class Field(Component):
|
||||
self.add_sw_access(obj)
|
||||
|
||||
def add_sw_access(self, obj, alias = False):
|
||||
access_rtl = dict()
|
||||
access_rtl = {}
|
||||
|
||||
if alias:
|
||||
owning_addrmap, full_path, path, path_underscored =\
|
||||
@ -156,7 +156,7 @@ class Field(Component):
|
||||
else:
|
||||
# Normal write
|
||||
# If field spans multiple bytes, every byte shall have a seperate enable!
|
||||
for j, i in enumerate(range(self.lsbyte, self.msbyte+1)):
|
||||
for i in range(self.lsbyte, self.msbyte+1):
|
||||
msb_bus = 8*(i+1)-1 if i != self.msbyte else obj.msb
|
||||
lsb_bus = 8*i if i != self.lsbyte else obj.inst.lsb
|
||||
|
||||
@ -315,8 +315,8 @@ class Field(Component):
|
||||
|
||||
if obj_incr_width:
|
||||
self.logger.error(
|
||||
"The 'incrwidth' and 'incrvalue' properties are both "\
|
||||
"defined. This is not legal and the incrwidth property "\
|
||||
"The 'incrwidth' and 'incrvalue' properties are both "
|
||||
"defined. This is not legal and the incrwidth property "
|
||||
"will be ignored!")
|
||||
else:
|
||||
incr_value = self.get_signal_name(obj_incr_value)
|
||||
@ -324,14 +324,14 @@ class Field(Component):
|
||||
|
||||
if obj_incr_value.width > self.obj.width:
|
||||
self.logger.error(
|
||||
"Width of 'incr_value' signal '{}' is wider than current "\
|
||||
"counter field. This could potentially cause ugly errors.".format(
|
||||
obj_incr_value.get_path()))
|
||||
f"Width of 'incr_value' signal '{obj_incr_value.get_path()}' is "
|
||||
"wider than current counter field. This could potentiall cause "
|
||||
"ugly errors.")
|
||||
|
||||
if obj_incr_width:
|
||||
self.logger.error(
|
||||
"The 'incrwidth' and 'incrvalue' properties are both "\
|
||||
"defined. This is not legal and the incrwidth property "\
|
||||
"The 'incrwidth' and 'incrvalue' properties are both "
|
||||
"defined. This is not legal and the incrwidth property "
|
||||
"will be ignored!")
|
||||
|
||||
|
||||
@ -383,8 +383,8 @@ class Field(Component):
|
||||
|
||||
if obj_decr_width:
|
||||
self.logger.error(
|
||||
"The 'decrwidth' and 'decrvalue' properties are both "\
|
||||
"defined. This is not legal and the decrwidth property "\
|
||||
"The 'decrwidth' and 'decrvalue' properties are both "
|
||||
"defined. This is not legal and the decrwidth property "
|
||||
"will be ignored!")
|
||||
else:
|
||||
decr_value = self.get_signal_name(obj_decr_value)
|
||||
@ -392,14 +392,14 @@ class Field(Component):
|
||||
|
||||
if obj_decr_value.width > self.obj.width:
|
||||
self.logger.error(
|
||||
"Width of 'decr_value' signal '{}' is wider than current "\
|
||||
"counter field. This could potentially cause ugly errors.".format(
|
||||
obj_decr_value.get_path()))
|
||||
f"Width of 'decr_value' signal '{obj_decr_value.get_path()}' is "
|
||||
"wider than current counter field. This could potentiall cause "
|
||||
"ugly errors.")
|
||||
|
||||
if obj_decr_width:
|
||||
self.logger.error(
|
||||
"The 'decrwidth' and 'decrvalue' properties are both "\
|
||||
"defined. This is not legal and the decrwidth property "\
|
||||
"The 'decrwidth' and 'decrvalue' properties are both "
|
||||
"defined. This is not legal and the decrwidth property "
|
||||
"will be ignored!")
|
||||
|
||||
|
||||
@ -449,10 +449,10 @@ class Field(Component):
|
||||
|
||||
try:
|
||||
if incr.width > 0:
|
||||
self.logger.error("Increment signal '{}' is wider than 1-bit. "\
|
||||
"This might result in unwanted behavior and "\
|
||||
"will also cause Lint-errors.".format(
|
||||
incr.inst_name))
|
||||
self.logger.error(
|
||||
f"Increment signal '{incr.inst_name}' is wider than "
|
||||
"1 bit. This might result in unwanted behavior and "
|
||||
"will also cause Lint-errors.")
|
||||
except AttributeError:
|
||||
# 'PropRef_overflow' object has no attribute 'width'
|
||||
pass
|
||||
@ -490,10 +490,10 @@ class Field(Component):
|
||||
|
||||
try:
|
||||
if decr.width > 0:
|
||||
self.logger.error("Decrement signal '{}' is wider than 1-bit. "\
|
||||
"This might result in unwanted behavior and "\
|
||||
"will also cause Lint-errors.".format(
|
||||
decr.inst_name))
|
||||
self.logger.error(
|
||||
f"Decrement signal '{decr.inst_name}' is wider than "
|
||||
"1 bit. This might result in unwanted behavior and "
|
||||
"will also cause Lint-errors.")
|
||||
except AttributeError:
|
||||
# 'PropRef_underflow' object has no attribute 'width'
|
||||
pass
|
||||
@ -627,7 +627,7 @@ class Field(Component):
|
||||
if self.obj.get_property('swmod'):
|
||||
self.logger.debug("Field has swmod property")
|
||||
|
||||
swmod_assigns = list()
|
||||
swmod_assigns = []
|
||||
|
||||
# Check if read side-effects are defined.
|
||||
if self.obj.get_property('onread'):
|
||||
@ -982,7 +982,7 @@ class Field(Component):
|
||||
'enable_mask_start': enable_mask_start_rtl,
|
||||
'enable_mask_end': enable_mask_end_rtl,
|
||||
'idx': enable_mask_idx,
|
||||
'constant': "{{{}{{1'b1}}}}".format(self.obj.width)
|
||||
'constant': f"{{{self.obj.width}{{1'b1}}}}"
|
||||
if not enable_mask else "1'b1"
|
||||
}
|
||||
)
|
||||
@ -997,7 +997,7 @@ class Field(Component):
|
||||
'enable_mask_start': enable_mask_start_rtl,
|
||||
'enable_mask_end': enable_mask_end_rtl,
|
||||
'idx': enable_mask_idx,
|
||||
'constant': "{{{}{{1'b0}}}}".format(self.obj.width)
|
||||
'constant': f"{{{self.obj.width}{{1'b0}}}}"
|
||||
if not enable_mask else "1'b0"
|
||||
}
|
||||
)
|
||||
@ -1024,7 +1024,7 @@ class Field(Component):
|
||||
# Create bit-wise mask so that outside logic knows what
|
||||
# bits it may change
|
||||
mask = []
|
||||
for j, byte_idx in enumerate(range(self.msbyte, self.lsbyte-1, -1)):
|
||||
for byte_idx in range(self.msbyte, self.lsbyte-1, -1):
|
||||
if byte_idx == self.lsbyte:
|
||||
width = (self.lsbyte+1)*8 - self.lsb
|
||||
elif byte_idx == self.msbyte:
|
||||
@ -1183,7 +1183,7 @@ class Field(Component):
|
||||
# kill the try block in most cases
|
||||
parent_scope = enum.get_parent_scope()
|
||||
|
||||
self.logger.debug("Starting to parse '{}'".format(enum))
|
||||
self.logger.debug(f"Starting to parse '{enum}'")
|
||||
|
||||
if isinstance(parent_scope, Reg):
|
||||
enum_name = '__'.join([enum.get_scope_path().split('::')[-1], enum.__name__])
|
||||
@ -1219,12 +1219,12 @@ class Field(Component):
|
||||
self.field_type =\
|
||||
'::'.join(['_'.join([scope, 'pkg']), enum_name])
|
||||
|
||||
self.logger.info("Parsed enum '{}'".format(enum_name))
|
||||
self.logger.info(f"Parsed enum '{enum_name}'")
|
||||
|
||||
except AttributeError:
|
||||
# In case of an AttributeError, the encode property is None. Hence,
|
||||
# the field has a simple width
|
||||
self.field_type = 'logic [{}:0]'.format(self.obj.width-1)
|
||||
self.field_type = f"logic [{self.obj.width-1}:0]"
|
||||
|
||||
def __process_variables(self, obj: FieldNode, array_dimensions: list, glbl_settings: dict):
|
||||
# Create full name
|
||||
@ -1248,7 +1248,7 @@ class Field(Component):
|
||||
self.total_dimensions = len(self.total_array_dimensions)
|
||||
|
||||
# Calculate how many genvars shall be added
|
||||
genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(len(array_dimensions))]
|
||||
genvars = [f"[gv_{chr(97+i)}]" for i in range(len(array_dimensions))]
|
||||
self.genvars_str = ''.join(genvars)
|
||||
|
||||
# Write enable
|
||||
@ -1285,18 +1285,23 @@ class Field(Component):
|
||||
obj.get_property('reset')
|
||||
|
||||
# Define dict that holds all RTL
|
||||
self.access_rtl = dict()
|
||||
self.access_rtl = {}
|
||||
self.access_rtl['else'] = (["else"], False)
|
||||
self.access_rtl[''] = ([''], False)
|
||||
|
||||
def summary(self):
|
||||
# Additional flags that are set
|
||||
misc_flags = set(self.obj.list_properties())
|
||||
# Use list, rather than set, to ensure the order stays the same
|
||||
# when compiled multiple times
|
||||
misc_flags = list(self.obj.list_properties())
|
||||
|
||||
# Remove some flags that are not interesting
|
||||
# or that are listed elsewhere
|
||||
misc_flags.discard('hw')
|
||||
misc_flags.discard('reset')
|
||||
for rdl_property in ('hw', 'reset'):
|
||||
try:
|
||||
misc_flags.remove(rdl_property)
|
||||
except ValueError:
|
||||
pass
|
||||
|
||||
precedence = self.obj.get_property('precedence')
|
||||
|
||||
|
||||
@ -1,11 +1,9 @@
|
||||
import re
|
||||
import importlib.resources as pkg_resources
|
||||
import sys
|
||||
import math
|
||||
import yaml
|
||||
|
||||
from systemrdl import node
|
||||
from systemrdl.node import FieldNode
|
||||
from systemrdl.rdltypes import AccessType
|
||||
|
||||
# Local packages
|
||||
@ -192,10 +190,8 @@ class Memory(Component):
|
||||
]
|
||||
|
||||
def get_signal_instantiations_list(self):
|
||||
dict_list = [(key, value) for (key, value) in self.get_signals().items()]
|
||||
|
||||
dict_list = list(self.get_signals().items())
|
||||
signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
|
||||
|
||||
name_width = min(max([len(key) for (key, _) in dict_list]), 40)
|
||||
|
||||
return [Memory.templ_dict['signal_declaration'].format(
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
import re
|
||||
import importlib.resources as pkg_resources
|
||||
import sys
|
||||
import math
|
||||
@ -35,8 +34,8 @@ class RegFile(Component):
|
||||
# Empty dictionary of register objects
|
||||
# We need a dictionary since it might be required to access the objects later
|
||||
# by name (for example, in case of aliases)
|
||||
self.registers = dict()
|
||||
self.regfiles = dict()
|
||||
self.registers = {}
|
||||
self.regfiles = {}
|
||||
|
||||
# Set object to 0 for easy addressing
|
||||
self.obj.current_idx = [0]
|
||||
@ -216,12 +215,12 @@ class RegFile(Component):
|
||||
|
||||
# First go through all registers in this scope to generate a package
|
||||
package_rtl = []
|
||||
enum_rtl = dict()
|
||||
rtl_return = list()
|
||||
enum_rtl = {}
|
||||
rtl_return = []
|
||||
|
||||
# Need to keep track of enum names since they shall be unique
|
||||
# per scope
|
||||
enum_members = dict()
|
||||
enum_members = {}
|
||||
|
||||
for i in self.registers.values():
|
||||
for key, value in i.get_typedefs().items():
|
||||
|
||||
@ -2,7 +2,6 @@ import importlib.resources as pkg_resources
|
||||
import math
|
||||
import sys
|
||||
import yaml
|
||||
import itertools
|
||||
|
||||
from systemrdl import node
|
||||
|
||||
@ -52,9 +51,11 @@ class Register(Component):
|
||||
def create_rtl(self):
|
||||
# Create RTL of children
|
||||
if self.config['external']:
|
||||
[x.create_external_rtl() for x in self.children.values()]
|
||||
for child in self.children.values():
|
||||
child.create_external_rtl()
|
||||
else:
|
||||
[x.create_internal_rtl() for x in self.children.values()]
|
||||
for child in self.children.values():
|
||||
child.create_internal_rtl()
|
||||
|
||||
# Create generate block for register and add comment
|
||||
if self.dimensions and not self.generate_active:
|
||||
@ -166,14 +167,16 @@ class Register(Component):
|
||||
list_of_fields.append(
|
||||
f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
|
||||
|
||||
list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str))
|
||||
list_of_fields.append(f"{field.path_underscored}_q{self.genvars_str}")
|
||||
|
||||
# Add to appropriate bytes
|
||||
[bytes_read.add(x) for x in range(field.lsbyte, field.msbyte+1)]
|
||||
for byte in range(field.lsbyte, field.msbyte+1):
|
||||
bytes_read.add(byte)
|
||||
|
||||
if na_map[0] in field.writable_by:
|
||||
# Add to appropriate bytes
|
||||
[bytes_written.add(x) for x in range(field.lsbyte, field.msbyte+1)]
|
||||
for byte in range(field.lsbyte, field.msbyte+1):
|
||||
bytes_written.add(byte)
|
||||
|
||||
empty_bits = accesswidth - current_bit + 1
|
||||
|
||||
@ -208,8 +211,8 @@ class Register(Component):
|
||||
# an error.
|
||||
#
|
||||
# Furthermore, consider an error indication that is set for external registers
|
||||
bytes_read_format = ["b2r.byte_en[{}]".format(x) for x in list(map(str, bytes_read))]
|
||||
bytes_written_format = ["b2r.byte_en[{}]".format(x) for x in list(map(str, bytes_written))]
|
||||
bytes_read_format = [f"b2r.byte_en[{x}]" for x in list(map(str, bytes_read))]
|
||||
bytes_written_format = [f"b2r.byte_en[{x}]" for x in list(map(str, bytes_written))]
|
||||
|
||||
sw_err_condition_vec = []
|
||||
|
||||
@ -331,7 +334,7 @@ class Register(Component):
|
||||
vec[depth] = i
|
||||
|
||||
if depth == len(dimensions) - 1:
|
||||
yield '[{}]'.format(']['.join(map(str, vec)))
|
||||
yield f"[{']['.join(map(str, vec))}]"
|
||||
else:
|
||||
yield from Register.eval_genvars(vec, depth+1, dimensions)
|
||||
|
||||
@ -346,11 +349,11 @@ class Register(Component):
|
||||
else:
|
||||
access_wire_assign_field = 'access_wire_assign_1_dim'
|
||||
|
||||
for i, x in enumerate(self.name_addr_mappings):
|
||||
for i, name_addr_map in enumerate(self.name_addr_mappings):
|
||||
self.rtl_header.append(
|
||||
self.process_yaml(
|
||||
Register.templ_dict['access_wire_comment'],
|
||||
{'path': x[0],
|
||||
{'path': name_addr_map[0],
|
||||
'alias': '(alias)' if i > 0 else '',
|
||||
}
|
||||
)
|
||||
@ -359,8 +362,8 @@ class Register(Component):
|
||||
self.rtl_header.append(
|
||||
self.process_yaml(
|
||||
Register.templ_dict[access_wire_assign_field],
|
||||
{'path': x[0],
|
||||
'addr': x[1],
|
||||
{'path': name_addr_map[0],
|
||||
'addr': name_addr_map[1],
|
||||
'genvars': self.genvars_str,
|
||||
'genvars_sum': self.genvars_sum_str,
|
||||
'depth': self.depth,
|
||||
@ -376,8 +379,8 @@ class Register(Component):
|
||||
self.rtl_header.append(
|
||||
self.process_yaml(
|
||||
Register.templ_dict['read_wire_assign'],
|
||||
{'path': x[0],
|
||||
'addr': x[1],
|
||||
{'path': name_addr_map[0],
|
||||
'addr': name_addr_map[1],
|
||||
'genvars': self.genvars_str,
|
||||
'genvars_sum': self.genvars_sum_str,
|
||||
'depth': self.depth,
|
||||
@ -388,7 +391,7 @@ class Register(Component):
|
||||
self.rtl_header.append(
|
||||
self.process_yaml(
|
||||
Register.templ_dict['read_wire_assign_0'],
|
||||
{'path': x[0],
|
||||
{'path': name_addr_map[0],
|
||||
'genvars': self.genvars_str,
|
||||
}
|
||||
)
|
||||
@ -402,8 +405,8 @@ class Register(Component):
|
||||
self.rtl_header.append(
|
||||
self.process_yaml(
|
||||
Register.templ_dict['write_wire_assign'],
|
||||
{'path': x[0],
|
||||
'addr': x[1],
|
||||
{'path': name_addr_map[0],
|
||||
'addr': name_addr_map[1],
|
||||
'genvars': self.genvars_str,
|
||||
'genvars_sum': self.genvars_sum_str,
|
||||
'depth': self.depth,
|
||||
@ -414,7 +417,7 @@ class Register(Component):
|
||||
self.rtl_header.append(
|
||||
self.process_yaml(
|
||||
Register.templ_dict['write_wire_assign_0'],
|
||||
{'path': x[0],
|
||||
{'path': name_addr_map[0],
|
||||
'genvars': self.genvars_str,
|
||||
}
|
||||
)
|
||||
@ -446,7 +449,7 @@ class Register(Component):
|
||||
]
|
||||
|
||||
def get_signal_instantiations_list(self):
|
||||
dict_list = [(key, value) for (key, value) in self.get_signals().items()]
|
||||
dict_list = list(self.get_signals().items())
|
||||
|
||||
signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
|
||||
|
||||
@ -472,13 +475,12 @@ class Register(Component):
|
||||
try:
|
||||
self.children[field_range].add_sw_access(field, alias=True)
|
||||
except KeyError:
|
||||
self.logger.fatal("Range of field '{}' in alias register '{}' does "
|
||||
"not correspond to range of field in original "
|
||||
"register '{}'. This is illegal according to 10.5.1 b)"
|
||||
"of the SystemRDL 2.0 LRM.". format(
|
||||
field.inst_name,
|
||||
obj.inst_name,
|
||||
self.name))
|
||||
self.logger.fatal(
|
||||
f"Range of field '{field.inst_name}' in alias register "
|
||||
f"'{obj.inst_name}' does not correspond to range of field "
|
||||
f"in original register '{self.name}'. This is illegal "
|
||||
"according to 10.5.1 b) of the SystemRDL 2.0 LRM.")
|
||||
|
||||
sys.exit(1)
|
||||
|
||||
# Add name to list
|
||||
@ -541,7 +543,7 @@ class Register(Component):
|
||||
self.dimensions = len(self.array_dimensions)
|
||||
|
||||
# Calculate how many genvars shall be added
|
||||
genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(self.total_dimensions)]
|
||||
genvars = [f"[gv_{chr(97+i)}]" for i in range(self.total_dimensions)]
|
||||
self.genvars_str = ''.join(genvars)
|
||||
|
||||
# Determine value to compare address with
|
||||
@ -564,9 +566,9 @@ class Register(Component):
|
||||
genvars_sum_vectorized.pop()
|
||||
|
||||
self.logger.debug(
|
||||
"Multidimensional with dimensions '{}' and stride '{}'".format(
|
||||
self.total_array_dimensions,
|
||||
self.total_stride))
|
||||
f"Multidimensional with dimensions '{self.total_array_dimensions}' "
|
||||
f"and stride '{self.total_stride}'")
|
||||
|
||||
except TypeError:
|
||||
self.logger.debug(
|
||||
"Caught expected TypeError because self.total_stride is empty")
|
||||
|
||||
@ -3,7 +3,6 @@
|
||||
# Standard modules
|
||||
import sys
|
||||
import time
|
||||
import os
|
||||
import importlib.resources as pkg_resources
|
||||
|
||||
# Imported modules
|
||||
@ -42,16 +41,16 @@ if __name__ == "__main__":
|
||||
except RDLCompileError:
|
||||
sys.exit(1)
|
||||
except FileNotFoundError:
|
||||
logger.fatal("Could not find '{}'".format(input_file))
|
||||
logger.fatal(f"Could not find '{input_file}'")
|
||||
sys.exit(1)
|
||||
|
||||
addrmap = AddrMap(root.top, config)
|
||||
|
||||
# Save RTL to file
|
||||
# Start out with addrmap
|
||||
out_addrmap_file = "{}/{}.sv".format(config['output_dir'], addrmap.name)
|
||||
out_addrmap_file = f"{config['output_dir']}/{addrmap.name}.sv"
|
||||
|
||||
with open(out_addrmap_file, 'w') as file:
|
||||
with open(out_addrmap_file, 'w', encoding='UTF-8') as file:
|
||||
print(
|
||||
addrmap.get_rtl(
|
||||
tab_width=config['tab_width'],
|
||||
@ -60,7 +59,7 @@ if __name__ == "__main__":
|
||||
file=file
|
||||
)
|
||||
|
||||
logger.info('Succesfully created "{}"'.format(out_addrmap_file))
|
||||
logger.info("Succesfully created '{out_addrmap_file}'")
|
||||
|
||||
# Start grabbing packages. This returns a dictionary for the main addrmap
|
||||
# and all it's child regfiles/addrmaps
|
||||
@ -69,25 +68,25 @@ if __name__ == "__main__":
|
||||
real_tabs=config['real_tabs']
|
||||
).items():
|
||||
if value:
|
||||
with open('{}/{}_pkg.sv'.format(config['output_dir'], key), 'w') as file:
|
||||
with open(f"{config['output_dir']}/{key}_pkg.sv", 'w', encoding="UTF-8") as file:
|
||||
print(value, file=file)
|
||||
|
||||
# Copy over widget RTL from widget directory
|
||||
widget_rtl = pkg_resources.read_text(widgets, 'srdl2sv_{}.sv'.format(config['bus']))
|
||||
widget_rtl = pkg_resources.read_text(widgets, f"srdl2sv_{config['bus']}.sv")
|
||||
|
||||
out_widget_file = "{}/srdl2sv_{}.sv".format(config['output_dir'], config['bus'])
|
||||
out_widget_file = f"{config['output_dir']}/srdl2sv_{config['bus']}.sv"
|
||||
|
||||
with open(out_widget_file, 'w') as file:
|
||||
with open(out_widget_file, 'w', encoding="UTF-8") as file:
|
||||
print(widget_rtl, file=file)
|
||||
|
||||
logger.info("Selected, implemented, and copied '{}' widget".format(config['bus']))
|
||||
logger.info(f"Selected, implemented, and copied '{config['bus']}' widget")
|
||||
|
||||
# Copy over generic srdl2sv_interface_pkg
|
||||
widget_if_rtl = pkg_resources.read_text(widgets, 'srdl2sv_if_pkg.sv')
|
||||
|
||||
out_if_file = "{}/srdl2sv_if_pkg.sv".format(config['output_dir'])
|
||||
out_if_file = f"{config['output_dir']}/srdl2sv_if_pkg.sv"
|
||||
|
||||
with open(out_if_file, 'w') as file:
|
||||
with open(out_if_file, 'w', encoding="UTF-8") as file:
|
||||
widget_if_rtl_parsed = widget_if_rtl.format(
|
||||
regwidth_bit = addrmap.get_regwidth() - 1,
|
||||
regwidth_byte = int(addrmap.get_regwidth() / 8) - 1,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user