Fix bug in external read-interface

In dc37c879, some properties got saved in self.properties of a
Component. In that commit, self.properties['sw_rd'] never got set.
For that reason, external registers with a read-interface were broken.

srdl2sv/components/addrmap.py

@@ -270,7 +270,7 @@ class AddrMap(Component):
 
         return self.process_yaml(
             self.widget_templ_dict['module_instantiation'],
-            {'bus_width': self.regwidth}
+            {'bus_width': self.regwidth-1}
         )
 
 

srdl2sv/components/field.py

@@ -72,13 +72,12 @@ class Field(Component):
         # Define software access (if applicable)
         access_rtl['sw_write'] = ([], False)
 
-        if obj.get_property('sw') in (AccessType.rw, AccessType.w):
+        if self.properties['sw_wr']:
             # Append to list of registers that can write
             self.writable_by.add(path_wo_field)
 
             # This will need a wire to indicate that a write is taking place
             self.properties['sw_wr_wire'] = True
-            self.properties['sw_wr'] = True
 
             swwe = obj.get_property('swwe')
             swwel = obj.get_property('swwel')
@@ -1232,6 +1231,10 @@ class Field(Component):
         self.path_underscored_vec = []
         self.path_wo_field_vec = []
 
+        # Set some properties that always must be known
+        self.properties['sw_wr'] = obj.get_property('sw') in (AccessType.rw, AccessType.w)
+        self.properties['sw_rd'] = obj.get_property('sw') in (AccessType.rw, AccessType.r)
+
         # Save dimensions of unpacked dimension
         self.array_dimensions = array_dimensions
         self.total_array_dimensions = array_dimensions

srdl2sv/components/templates/fields.yaml

@@ -420,9 +420,9 @@ external_rd_assignments:
         - name: '{path}_ext_r_data'
           signal_type: '{field_type}'
         - name: '{path}_ext_r_ack'
-          signal_type: 'logic'
+          signal_type: ''
         - name: '{path}_ext_r_err'
-          signal_type: 'logic'
+          signal_type: ''
     output_ports:
         - name: '{path}_ext_r_req'
           signal_type: 'logic'
@@ -461,9 +461,9 @@ external_wr_assignments:
           signal_type: 'logic [{width}:0]'
     input_ports:
         - name: '{path}_ext_w_ack'
-          signal_type: 'logic'
+          signal_type: ''
         - name: '{path}_ext_w_err'
-          signal_type: 'logic'
+          signal_type: ''
 external_wr_mask_segment:
     rtl: |-
         {{{width}{{b2r.byte_en[{idx}]}}}}

srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml

@@ -56,7 +56,7 @@ module_instantiation:
         - name: 'HTRANS'
           signal_type: '[1:0]'
         - name: 'HWDATA'
-          signal_type: '[{bus_width}-1:0]'
+          signal_type: '[{bus_width}:0]'
         - name: 'HSEL'
           signal_type: ''
     output_ports:
@@ -65,4 +65,4 @@ module_instantiation:
         - name: 'HRESP'
           signal_type: ''
         - name: 'HRDATA'
-          signal_type: '[{bus_width}-1:0]'
+          signal_type: '[{bus_width}:0]'