From b89bf3663f051fabd31ca250ad260f3b89ace6b8 Mon Sep 17 00:00:00 2001 From: Dennis Date: Sun, 12 Sep 2021 16:44:37 -0700 Subject: [PATCH] Fix issue with read-mux assignment for multidimensional registers --- srdl2sv/components/register.py | 2 +- srdl2sv/components/templates/register.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py index c9074d4..8ff47aa 100644 --- a/srdl2sv/components/register.py +++ b/srdl2sv/components/register.py @@ -117,7 +117,7 @@ class Register(Component): if empty_bits > 0: list_of_fields.append("{}'b0".format(empty_bits)) - list_of_fields.append("{}_q".format(field.path_underscored)) + list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str)) # Add to appropriate bytes [bytes_read.add(x) for x in range(field.lsbyte, field.msbyte+1)] diff --git a/srdl2sv/components/templates/register.yaml b/srdl2sv/components/templates/register.yaml index d3a47f4..7394346 100644 --- a/srdl2sv/components/templates/register.yaml +++ b/srdl2sv/components/templates/register.yaml @@ -83,7 +83,7 @@ sw_data_assignment: * Assign all fields to signal to Mux * **************************************/ // Assign all fields. Fields that are not readable are tied to 0. - assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}{genvars}}}; + assign {sw_data_assignment_var_name}{genvars} = {{{list_of_fields}}}; // Internal registers are ready immediately assign {sw_rdy_assignment_var_name}{genvars} = {rdy_condition};