From baf08d2343820d94a5e2c121efb9306dbdc27ba1 Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Fri, 25 Jun 2021 11:50:06 +0200
Subject: [PATCH] Add bus_clk/bus_rst_n ports to widget (rather than (only)
 reg_clk)

---
 srdl2sv/components/widgets/amba3ahblite.sv   | 3 ++-
 srdl2sv/components/widgets/amba3ahblite.yaml | 5 +++--
 srdl2sv/main.py                              | 3 +++
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/srdl2sv/components/widgets/amba3ahblite.sv b/srdl2sv/components/widgets/amba3ahblite.sv
index 1571570..49aaffc 100644
--- a/srdl2sv/components/widgets/amba3ahblite.sv
+++ b/srdl2sv/components/widgets/amba3ahblite.sv
@@ -1,7 +1,8 @@
 module amba3ahblite_widget
 (
     // Register clock
-    input         reg_clk,
+    input         bus_clk,
+    input         bus_rst_n,
 
     // Outputs to internal logic
     output [31:0] addr,
diff --git a/srdl2sv/components/widgets/amba3ahblite.yaml b/srdl2sv/components/widgets/amba3ahblite.yaml
index 8c55c0c..14d6382 100644
--- a/srdl2sv/components/widgets/amba3ahblite.yaml
+++ b/srdl2sv/components/widgets/amba3ahblite.yaml
@@ -6,8 +6,9 @@ module_instantiation:
          ****************************/
         amba3ahblite_widget
         amba3ahblite_widget_inst
-            (// Register clock
-             .reg_clk,
+            (// Clocks & Resets
+             .bus_clk,
+             .bus_rst_n,
 
              // Outputs to internal logic
              .addr,
diff --git a/srdl2sv/main.py b/srdl2sv/main.py
index 66f47d7..e9f2b17 100755
--- a/srdl2sv/main.py
+++ b/srdl2sv/main.py
@@ -85,4 +85,7 @@ if __name__ == "__main__":
     with open(out_widget_file, 'w') as file:
         file.write(widget_rtl)
 
+    logger.info("Selected, implemented, and copied '{}' widget".format(config['bus']))
+
+    # Print elapsed time
     logger.info("Elapsed time: %f seconds", time.time() - start)