Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-12-22 06:58:41 +00:00
Code Issues Projects Releases Wiki Activity

Add hwset & hwclr properties

Browse Source
This commit is contained in:
Dennis Potter 2021-06-28 00:37:54 +02:00
parent 9385f59ac7
commit c00550a166
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 44 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
srdl2sv/components/field.py
View File

@ -557,6 +557,30 @@ class Field(Component):
else:
self.access_rtl['hw_write'] = ([], False)
# Check if the hwset or hwclr option is set
if self.obj.get_property('hwset'):
self.access_rtl['hw_setclr'] = ([
self.process_yaml(
Field.templ_dict['hw_access_hwset'],
{'path': self.path_underscored,
'genvars': self.genvars_str,
'width': self.obj.width}
)
],
False)
elif self.obj.get_property('hwclr'):
self.access_rtl['hw_setclr'] = ([
self.process_yaml(
Field.templ_dict['hw_access_hwclr'],
{'path': self.path_underscored,
'genvars': self.genvars_str,
'width': self.obj.width}
)
],
False)
else:
self.access_rtl['hw_setclr'] = ([], False)
# Hookup flop to output port in case register is readable by hardware
if self.obj.get_property('hw') in (AccessType.rw, AccessType.r):
# Connect flops to output port
@ -581,11 +605,13 @@ class Field(Component):
'sw_write',
'sw_read',
'hw_write',
'hw_setclr',
'singlepulse'
]
else:
order_list = [
'hw_write',
'hw_setclr',
'sw_write',
'sw_read',
'singlepulse'

18
srdl2sv/components/templates/fields.yaml
View File

@ -45,6 +45,24 @@ hw_access_we_wel:
hw_access_no_we_wel:
rtl: |-
// we or wel property not set
hw_access_hwset:
rtl: |-
if ({path}_hwset{genvars})
begin
{path}_q{genvars} <= {{{width}{{1'b1}}}};
end
input_ports:
- name: '{path}_hwset'
signal_type: 'logic'
hw_access_hwclr:
rtl: |-
if ({path}_hwclr{genvars})
begin
{path}_q{genvars} <= {{{width}{{1'b0}}}};
end
input_ports:
- name: '{path}_hwclr'
signal_type: 'logic'
hw_access_field:
rtl: |-
begin