From c5755bf104e8e61276c36b4af434f6e9f93f958d Mon Sep 17 00:00:00 2001
From: Dennis <dennis@dennispotter.eu>
Date: Mon, 17 May 2021 00:15:43 +0200
Subject: [PATCH] Removed genvars in case only 1 dimension with 1 entry is used

---
 srdl2sv/components/addrmap.py            | 12 +++++++++---
 srdl2sv/components/component.py          |  6 ------
 srdl2sv/components/register.py           | 11 ++++++++---
 srdl2sv/components/templates/fields.yaml |  2 +-
 srdl2sv/components/templates/regs.yaml   |  5 ++++-
 5 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py
index 758bb32..c906a0f 100644
--- a/srdl2sv/components/addrmap.py
+++ b/srdl2sv/components/addrmap.py
@@ -8,7 +8,6 @@ from systemrdl.node import FieldNode
 # Local packages
 from components.component import Component
 from components.register import Register
-from log.log import create_logger
 from . import templates
 
 
@@ -64,14 +63,21 @@ class AddrMap(Component):
             AddrMap.templ_dict['input_port'].format(
                 name = x.name,
                 packed_dim = x.packed_dim,
-                unpacked_dim = '[{}]'.format(']['.join([str(y) for y in x.unpacked_dim])))
+                unpacked_dim = '[{}]'.format(
+                    ']['.join(
+                        [str(y) for y in x.unpacked_dim]))
+                    if x.unpacked_dim else '')
             for x in self.get_ports('input')]
+
         # Output ports
         output_ports_rtl = [
             AddrMap.templ_dict['output_port'].format(
                 name = x.name,
                 packed_dim = x.packed_dim,
-                unpacked_dim = '[{}]'.format(']['.join([str(y) for y in x.unpacked_dim])))
+                unpacked_dim = '[{}]'.format(
+                    ']['.join(
+                        [str(y) for y in x.unpacked_dim]))
+                    if x.unpacked_dim else '')
             for x in self.get_ports('output')]
 
         # Remove comma from last port entry
diff --git a/srdl2sv/components/component.py b/srdl2sv/components/component.py
index 6498ef8..7e9a694 100644
--- a/srdl2sv/components/component.py
+++ b/srdl2sv/components/component.py
@@ -124,9 +124,3 @@ class Component():
         name.append(split_name[1])
 
         return ''.join(name)
-
-
-
-
-
-
diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py
index a8bc5de..935317d 100644
--- a/srdl2sv/components/register.py
+++ b/srdl2sv/components/register.py
@@ -66,13 +66,18 @@ class Register(Component):
         # Assign variables from bus
         self.obj.current_idx = [0]
 
+        if self.dimensions:
+            rw_wire_assign_field = 'rw_wire_assign_multi_dim'
+        else:
+            rw_wire_assign_field = 'rw_wire_assign_1_dim'
+
         self.rtl_header.append(
-            Register.templ_dict['rw_wire_assign'].format(
+            Register.templ_dict[rw_wire_assign_field].format(
                 path = self.path,
                 addr = self.obj.absolute_address,
                 genvars = self.genvars_str,
                 genvars_sum =self.genvars_sum_str,
-                stride = self.obj.array_stride if self.obj.array_stride else '0',
+                stride = self.obj.array_stride,
                 depth = self.depth))
 
     def __process_variables(self, obj: node.RootNode):
@@ -96,7 +101,7 @@ class Register(Component):
             self.array_dimensions = self.obj.array_dimensions
         else:
             self.sel_arr = 'single'
-            self.array_dimensions = [1]
+            self.array_dimensions = []
 
         self.depth = '[{}]'.format(']['.join(f"{i}" for i in self.array_dimensions))
         self.dimensions = len(self.array_dimensions)
diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml
index 3c33f78..7be476a 100644
--- a/srdl2sv/components/templates/fields.yaml
+++ b/srdl2sv/components/templates/fields.yaml
@@ -95,5 +95,5 @@ singlepulse: |-
 out_port_assign: |-
 
     // Connect register to hardware output port
-    assign {path}_r{genvars} <= {path}_q{genvars};
+    assign {path}_r{genvars} = {path}_q{genvars};
 
diff --git a/srdl2sv/components/templates/regs.yaml b/srdl2sv/components/templates/regs.yaml
index aab8d68..559283b 100644
--- a/srdl2sv/components/templates/regs.yaml
+++ b/srdl2sv/components/templates/regs.yaml
@@ -2,7 +2,10 @@
 rw_wire_declare: |
     logic {path}_sw_wr {depth};
     logic {path}_sw_rd {depth};
-rw_wire_assign: |
+rw_wire_assign_1_dim: |
+    assign {path}_sw_wr{genvars} = addr == {addr} && r_vld;
+    assign {path}_sw_rd{genvars} = addr == {addr} && w_vld;
+rw_wire_assign_multi_dim: |
     assign {path}_sw_wr{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && r_vld;
     assign {path}_sw_rd{genvars} = addr == ({addr}+({genvars_sum})*{stride}) && w_vld;
 reg_comment: |-