From cc0d961a4182d393f17c6880c43e041de488b1f2 Mon Sep 17 00:00:00 2001 From: Dennis Date: Tue, 2 Nov 2021 23:28:58 -0700 Subject: [PATCH] Regenerate examples with changes from 95b9a5a4 and 85dc719 --- examples/enums/srdl2sv_out/enums.sv | 12 +++---- .../srdl2sv_out/hierarchical_regfiles.sv | 14 ++++---- .../srdl2sv_out/interrupt_hierarchy.sv | 36 ++----------------- .../srdl2sv_out/simple_rw_reg.sv | 10 +++--- 4 files changed, 20 insertions(+), 52 deletions(-) diff --git a/examples/enums/srdl2sv_out/enums.sv b/examples/enums/srdl2sv_out/enums.sv index 748c850..d733e17 100644 --- a/examples/enums/srdl2sv_out/enums.sv +++ b/examples/enums/srdl2sv_out/enums.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : October 31 2021 16:01:37 + * - Time : November 02 2021 23:27:37 * - Path : /home/dpotter/srdl2sv/examples/enums * - RDL file : ['enums.rdl'] * - Hostname : ArchXPS @@ -29,7 +29,7 @@ * - * * Commandline arguments to srdl2sv: - * - Ouput Directory : ./srdl2sv_out + * - Ouput Directory : srdl2sv_out * - Stream Log Level : INFO * - File Log Level : NONE * - Use Real Tabs : False @@ -239,7 +239,7 @@ assign regfile_1__reg_c_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign regfile_1__reg_c_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1]))); +assign regfile_1__reg_c_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[1:0])) || (widget_if.w_vld && (|widget_if.byte_en[1:0]))); /******************************************************************* /******************************************************************* @@ -329,7 +329,7 @@ assign regfile_1__reg_d_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign regfile_1__reg_d_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1]))); +assign regfile_1__reg_d_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[1:0])) || (widget_if.w_vld && (|widget_if.byte_en[1:0]))); /******************************************************************* /******************************************************************* @@ -419,7 +419,7 @@ assign reg_a_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign reg_a_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1]))); +assign reg_a_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[1:0])) || (widget_if.w_vld && (|widget_if.byte_en[1:0]))); /******************************************************************* /******************************************************************* @@ -509,7 +509,7 @@ assign reg_b_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign reg_b_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1]))); +assign reg_b_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[1:0])) || (widget_if.w_vld && (|widget_if.byte_en[1:0]))); // Read multiplexer always_comb diff --git a/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv b/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv index 139bc47..6fbe473 100644 --- a/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv +++ b/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : October 31 2021 15:59:23 + * - Time : November 02 2021 23:27:37 * - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles * - RDL file : ['hierarchical_regfiles.rdl'] * - Hostname : ArchXPS @@ -29,7 +29,7 @@ * - * * Commandline arguments to srdl2sv: - * - Ouput Directory : ./srdl2sv_out + * - Ouput Directory : srdl2sv_out * - Stream Log Level : INFO * - File Log Level : NONE * - Use Real Tabs : False @@ -254,7 +254,7 @@ assign regfile_1__reg_a_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign regfile_1__reg_a_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); +assign regfile_1__reg_a_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); /******************************************************************* /******************************************************************* @@ -348,7 +348,7 @@ assign regfile_1__reg_b_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign regfile_1__reg_b_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); +assign regfile_1__reg_b_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); /******************************************************************* ******************************************************************* * REGFILE : regfile_2 @@ -477,7 +477,7 @@ begin // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. - assign regfile_2__regfile_3__reg_d_err_mux_in[gv_a][gv_b][gv_c] = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); + assign regfile_2__regfile_3__reg_d_err_mux_in[gv_a][gv_b][gv_c] = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); end // of for loop with iterator gv_b end // of for loop with iterator gv_a @@ -564,7 +564,7 @@ begin // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. - assign regfile_2__reg_c_err_mux_in[gv_a] = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[2] || widget_if.byte_en[3]))); + assign regfile_2__reg_c_err_mux_in[gv_a] = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:2]))); end // of for loop with iterator gv_a endgenerate @@ -661,7 +661,7 @@ assign reg_e_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign reg_e_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); +assign reg_e_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); // Read multiplexer always_comb diff --git a/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv b/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv index 58ea83e..14f1b35 100644 --- a/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv +++ b/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : October 31 2021 15:59:28 + * - Time : November 02 2021 23:27:21 * - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy * - RDL file : ['interrupt_hierarchy.rdl'] * - Hostname : ArchXPS @@ -29,7 +29,7 @@ * - * * Commandline arguments to srdl2sv: - * - Ouput Directory : ./srdl2sv_out + * - Ouput Directory : srdl2sv_out * - Stream Log Level : INFO * - File Log Level : NONE * - Use Real Tabs : False @@ -202,9 +202,7 @@ begin if (block_a_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_a_int__crc_error_q[0:0] <= block_a_int__crc_error_q[0:0] & ~widget_if.w_data[0:0]; - end end else begin @@ -244,9 +242,7 @@ begin if (block_a_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_a_int__len_error_q[0:0] <= block_a_int__len_error_q[0:0] & ~widget_if.w_data[1:1]; - end end else begin @@ -286,9 +282,7 @@ begin if (block_a_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_a_int__multi_bit_ecc_error_q[0:0] <= block_a_int__multi_bit_ecc_error_q[0:0] & ~widget_if.w_data[2:2]; - end end else begin @@ -328,9 +322,7 @@ begin if (block_a_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_a_int__active_ecc_master_q[3:0] <= block_a_int__active_ecc_master_q[3:0] & ~widget_if.w_data[7:4]; - end end else if (|block_a_int__active_ecc_master_sticky_latch && !(|block_a_int__active_ecc_master_q)) @@ -645,9 +637,7 @@ begin if (block_b_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_b_int__crc_error_q[0:0] <= block_b_int__crc_error_q[0:0] & ~widget_if.w_data[0:0]; - end end else begin @@ -687,9 +677,7 @@ begin if (block_b_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_b_int__len_error_q[0:0] <= block_b_int__len_error_q[0:0] & ~widget_if.w_data[1:1]; - end end else begin @@ -729,9 +717,7 @@ begin if (block_b_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_b_int__multi_bit_ecc_error_q[0:0] <= block_b_int__multi_bit_ecc_error_q[0:0] & ~widget_if.w_data[2:2]; - end end else begin @@ -771,9 +757,7 @@ begin if (block_b_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_b_int__active_ecc_master_q[3:0] <= block_b_int__active_ecc_master_q[3:0] & ~widget_if.w_data[7:4]; - end end else if (|block_b_int__active_ecc_master_sticky_latch && !(|block_b_int__active_ecc_master_q)) @@ -1088,9 +1072,7 @@ begin if (block_c_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_c_int__crc_error_q[0:0] <= block_c_int__crc_error_q[0:0] & ~widget_if.w_data[0:0]; - end end else begin @@ -1130,9 +1112,7 @@ begin if (block_c_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_c_int__len_error_q[0:0] <= block_c_int__len_error_q[0:0] & ~widget_if.w_data[1:1]; - end end else begin @@ -1172,9 +1152,7 @@ begin if (block_c_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_c_int__multi_bit_ecc_error_q[0:0] <= block_c_int__multi_bit_ecc_error_q[0:0] & ~widget_if.w_data[2:2]; - end end else begin @@ -1214,9 +1192,7 @@ begin if (block_c_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_c_int__active_ecc_master_q[3:0] <= block_c_int__active_ecc_master_q[3:0] & ~widget_if.w_data[7:4]; - end end else if (|block_c_int__active_ecc_master_sticky_latch && !(|block_c_int__active_ecc_master_q)) @@ -1531,9 +1507,7 @@ begin if (block_d_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_d_int__crc_error_q[0:0] <= block_d_int__crc_error_q[0:0] & ~widget_if.w_data[0:0]; - end end else begin @@ -1573,9 +1547,7 @@ begin if (block_d_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_d_int__len_error_q[0:0] <= block_d_int__len_error_q[0:0] & ~widget_if.w_data[1:1]; - end end else begin @@ -1615,9 +1587,7 @@ begin if (block_d_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_d_int__multi_bit_ecc_error_q[0:0] <= block_d_int__multi_bit_ecc_error_q[0:0] & ~widget_if.w_data[2:2]; - end end else begin @@ -1657,9 +1627,7 @@ begin if (block_d_int_sw_wr) begin if (widget_if.byte_en[0]) // woclr property - begin block_d_int__active_ecc_master_q[3:0] <= block_d_int__active_ecc_master_q[3:0] & ~widget_if.w_data[7:4]; - end end else if (|block_d_int__active_ecc_master_sticky_latch && !(|block_d_int__active_ecc_master_q)) diff --git a/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv b/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv index 15912b7..0a0a2d0 100644 --- a/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv +++ b/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv @@ -20,7 +20,7 @@ * * Generation information: * - User: : dpotter - * - Time : October 31 2021 15:59:35 + * - Time : November 02 2021 23:27:37 * - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg * - RDL file : ['simple_rw_reg.rdl'] * - Hostname : ArchXPS @@ -29,7 +29,7 @@ * - * * Commandline arguments to srdl2sv: - * - Ouput Directory : ./srdl2sv_out + * - Ouput Directory : srdl2sv_out * - Stream Log Level : INFO * - File Log Level : NONE * - Use Real Tabs : False @@ -239,7 +239,7 @@ assign register_1d_rdy_mux_in = 1'b1; // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. -assign register_1d_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); +assign register_1d_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); /******************************************************************* /******************************************************************* @@ -336,7 +336,7 @@ begin // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. - assign register_2d_err_mux_in[gv_a] = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); + assign register_2d_err_mux_in[gv_a] = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); end // of for loop with iterator gv_a endgenerate @@ -439,7 +439,7 @@ begin // Return an error if *no* read and *no* write was succesful. If some bits // cannot be read/written but others are succesful, don't return and error // Hence, as long as one action can be succesful, no error will be returned. - assign register_3d_err_mux_in[gv_a][gv_b] = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); + assign register_3d_err_mux_in[gv_a][gv_b] = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0]))); end // of for loop with iterator gv_b end // of for loop with iterator gv_a