Buswidth is now variable, based on widest register

Fixes #2.

srdl2sv/cli/cli.py

@@ -142,6 +142,9 @@ class CliArguments():
         config['bus'] = args.bus
         config['list_args'].append('Register Bus Type: {}'.format(config['bus']))
 
+        if args.bus == 'amba3ahblite':
+            config['addrwidth'] = 32
+
         # Set version
         config['version'] = '0.01'
 

srdl2sv/components/addrmap.py

@@ -37,6 +37,7 @@ class AddrMap(Component):
         # by name (for example, in case of aliases)
         self.registers = dict()
         self.regfiles = dict()
+        self.regwidth = 0
 
         # Traverse through children
         for child in obj.children():
@@ -59,6 +60,16 @@ class AddrMap(Component):
                     self.registers[child.inst_name] = \
                         Register(child, [], [], config, glbl_settings)
 
+            try:
+                if (regwidth := self.registers[child.inst_name].get_regwidth()) > self.regwidth:
+                    self.regwidth = regwidth
+            except KeyError:
+                # Simply ignore nodes like SignalNodes
+                pass
+
+        self.logger.info("Detected maximum register width of whole addrmap to be '{}'".format(
+            self.regwidth))
+
         # Add registers to children. This must be done in a last step
         # to account for all possible alias combinations
         self.children = {**self.regfiles, **self.registers}
@@ -193,7 +204,6 @@ class AddrMap(Component):
         self.rtl_footer.append('endmodule')
 
     def __create_mux_string(self):
-        # TODO: Add variable for bus width
         # Define default case
         list_of_cases = [AddrMap.templ_dict['default_mux_case']['rtl']]
 
@@ -218,6 +228,7 @@ class AddrMap(Component):
                 list_of_cases.append(
                     AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
                         index = index,
+                        bus_width = self.config['addrwidth'],
                         r2b_data = r2b_data,
                         r2b_rdy = r2b_rdy,
                         r2b_err = r2b_err)
@@ -259,7 +270,7 @@ class AddrMap(Component):
 
         return self.process_yaml(
             self.widget_templ_dict['module_instantiation'],
-            # TODO: Add widths
+            {'bus_width': self.regwidth}
         )
 
 
@@ -356,4 +367,5 @@ class AddrMap(Component):
 
         return rtl_return
 
-
+    def get_regwidth(self) -> int:
+        return self.regwidth

srdl2sv/components/regfile.py

@@ -48,6 +48,7 @@ class RegFile(Component):
         else:
             self.generate_initiated = False
 
+        self.regwidth = 0
 
         # Traverse through children
         for child in obj.children():
@@ -83,6 +84,9 @@ class RegFile(Component):
                             config,
                             glbl_settings)
 
+            if (regwidth := self.registers[child.inst_name].get_regwidth()) > self.regwidth:
+                self.regwidth = regwidth
+
         # Add registers to children. This must be done in a last step
         # to account for all possible alias combinations
         self.children = {**self.regfiles, **self.registers}
@@ -270,3 +274,6 @@ class RegFile(Component):
         else:
             return {None: None}
 
+    def get_regwidth(self) -> int:
+        return self.regwidth
+

srdl2sv/components/register.py

@@ -498,3 +498,6 @@ class Register(Component):
         self.genvars_sum_str = ''.join(genvars_sum)
         self.genvars_sum_str_vectorized = ''.join(genvars_sum_vectorized)
 
+    def get_regwidth(self) -> int:
+        return self.obj.get_property('regwidth')
+

srdl2sv/components/templates/addrmap.yaml

@@ -127,7 +127,7 @@ default_mux_case:
         end
 list_of_mux_cases:
     rtl: |-
-        32'd{index}:
+        {bus_width}'d{index}:
         begin
         r2b.data = {r2b_data};
         r2b.err  = {r2b_err};

srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv

@@ -113,7 +113,7 @@ module srdl2sv_amba3ahblite
                 if (HREADYOUT)
                 begin
                     // Floor address. Sub-register access will be handled by byte-enables
-                    addr_q      <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
+                    addr_q      <= {HADDR[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
                     operation_q <= HWRITE ? WRITE : READ;
                 end
             end
@@ -121,7 +121,7 @@ module srdl2sv_amba3ahblite
             begin
                 if (HREADYOUT)
                     // Floor address. Sub-register access will be handled by byte-enables
-                    addr_q      <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
+                    addr_q      <= {HADDR[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
             end
         endcase
     end
@@ -237,10 +237,10 @@ module srdl2sv_amba3ahblite
     /***
      * Determine the number of active bytes
      ***/
-    logic [3:0] HSIZE_bitfielded;
-    logic [3:0] b2r_byte_en_next;
-    logic       b2r_w_vld_next;
-    logic       b2r_r_vld_next;
+    logic [BUS_BYTES-1:0] HSIZE_bitfielded;
+    logic [BUS_BYTES-1:0] b2r_byte_en_next;
+    logic                 b2r_w_vld_next;
+    logic                 b2r_r_vld_next;
 
     always_comb
     begin

srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml

@@ -13,7 +13,7 @@ module_instantiation:
          *******************************************************************/
         srdl2sv_amba3ahblite
              #(.FLOP_REGISTER_IF (0),
-               .BUS_BITS         (32))
+               .BUS_BITS         ({bus_width}))
         srdl2sv_amba3ahblite_inst
              (// Outputs to internal logic
              .b2r,
@@ -56,7 +56,7 @@ module_instantiation:
         - name: 'HTRANS'
           signal_type: '[1:0]'
         - name: 'HWDATA'
-          signal_type: '[31:0]'
+          signal_type: '[{bus_width}-1:0]'
         - name: 'HSEL'
           signal_type: ''
     output_ports:
@@ -65,4 +65,4 @@ module_instantiation:
         - name: 'HRESP'
           signal_type: ''
         - name: 'HRDATA'
-          signal_type: '[31:0]'
+          signal_type: '[{bus_width}-1:0]'

srdl2sv/components/widgets/srdl2sv_if_pkg.sv

@@ -1,17 +1,17 @@
 package srdl2sv_if_pkg;
 
-typedef struct packed { // .Verilator does not support unpacked structs in packages
-    logic [31:0] addr;
-    logic [31:0] data;
+typedef struct packed {{ // .Verilator does not support unpacked structs in packages
+    logic [{addrwidth}:0] addr;
+    logic [{regwidth_bit}:0] data;
     logic        w_vld;
     logic        r_vld;
-    logic [ 3:0] byte_en;
-} b2r_t;
+    logic [ {regwidth_byte}:0] byte_en;
+}} b2r_t;
 
-typedef struct packed { // .Verilator does not support unpacked structs in packages
-    logic [31:0] data;
+typedef struct packed {{ // .Verilator does not support unpacked structs in packages
+    logic [{regwidth_bit}:0] data;
     logic        rdy;
     logic        err;
-} r2b_t;
+}} r2b_t;
 
 endpackage

srdl2sv/main.py

@@ -97,7 +97,12 @@ if __name__ == "__main__":
     out_if_file = "{}/srdl2sv_if_pkg.sv".format(config['output_dir'])
 
     with open(out_if_file, 'w') as file:
-        print(widget_if_rtl,file=file)
+        widget_if_rtl_parsed = widget_if_rtl.format(
+            regwidth_bit = addrmap.get_regwidth() - 1,
+            regwidth_byte = int(addrmap.get_regwidth() / 8) - 1,
+            addrwidth = config['addrwidth'] - 1)
+
+        print(widget_if_rtl_parsed,file=file)
 
     logger.info("Copied 'srdl2sv_if_pkg.sv")
 

tests/systemrdl/simple_rw_reg.rdl

@@ -1,5 +1,6 @@
 addrmap simple_rw_reg {
     reg {
+        regwidth = 64;
         field {sw=rw; hw=rw;} f1 [15:0];
         field {sw=rw; hw=rw;} f2 [31:16];
     } register_0 [2];