parent
6359883c27
commit
d3bfdeb3f0
GPG Key ID:
186A8AD440942BAF
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@ -142,6 +142,9 @@ class CliArguments():
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config['bus'] = args.bus
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config['list_args'].append('Register Bus Type: {}'.format(config['bus']))
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if args.bus == 'amba3ahblite':
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config['addrwidth'] = 32
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# Set version
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config['version'] = '0.01'
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@ -37,6 +37,7 @@ class AddrMap(Component):
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# by name (for example, in case of aliases)
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self.registers = dict()
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self.regfiles = dict()
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self.regwidth = 0
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# Traverse through children
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for child in obj.children():
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@ -59,6 +60,16 @@ class AddrMap(Component):
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self.registers[child.inst_name] = \
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Register(child, [], [], config, glbl_settings)
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try:
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if (regwidth := self.registers[child.inst_name].get_regwidth()) > self.regwidth:
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self.regwidth = regwidth
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except KeyError:
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# Simply ignore nodes like SignalNodes
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pass
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self.logger.info("Detected maximum register width of whole addrmap to be '{}'".format(
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self.regwidth))
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# Add registers to children. This must be done in a last step
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# to account for all possible alias combinations
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self.children = {**self.regfiles, **self.registers}
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@ -193,7 +204,6 @@ class AddrMap(Component):
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self.rtl_footer.append('endmodule')
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def __create_mux_string(self):
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# TODO: Add variable for bus width
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# Define default case
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list_of_cases = [AddrMap.templ_dict['default_mux_case']['rtl']]
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@ -218,6 +228,7 @@ class AddrMap(Component):
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list_of_cases.append(
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AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
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index = index,
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bus_width = self.config['addrwidth'],
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r2b_data = r2b_data,
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r2b_rdy = r2b_rdy,
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r2b_err = r2b_err)
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@ -259,7 +270,7 @@ class AddrMap(Component):
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return self.process_yaml(
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self.widget_templ_dict['module_instantiation'],
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# TODO: Add widths
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{'bus_width': self.regwidth}
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)
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@ -356,4 +367,5 @@ class AddrMap(Component):
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return rtl_return
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def get_regwidth(self) -> int:
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return self.regwidth
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@ -48,6 +48,7 @@ class RegFile(Component):
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else:
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self.generate_initiated = False
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self.regwidth = 0
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# Traverse through children
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for child in obj.children():
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@ -83,6 +84,9 @@ class RegFile(Component):
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config,
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glbl_settings)
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if (regwidth := self.registers[child.inst_name].get_regwidth()) > self.regwidth:
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self.regwidth = regwidth
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# Add registers to children. This must be done in a last step
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# to account for all possible alias combinations
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self.children = {**self.regfiles, **self.registers}
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@ -270,3 +274,6 @@ class RegFile(Component):
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else:
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return {None: None}
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def get_regwidth(self) -> int:
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return self.regwidth
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@ -498,3 +498,6 @@ class Register(Component):
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self.genvars_sum_str = ''.join(genvars_sum)
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self.genvars_sum_str_vectorized = ''.join(genvars_sum_vectorized)
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def get_regwidth(self) -> int:
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return self.obj.get_property('regwidth')
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@ -127,7 +127,7 @@ default_mux_case:
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end
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list_of_mux_cases:
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rtl: |-
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32'd{index}:
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{bus_width}'d{index}:
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begin
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r2b.data = {r2b_data};
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r2b.err = {r2b_err};
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@ -113,7 +113,7 @@ module srdl2sv_amba3ahblite
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if (HREADYOUT)
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begin
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// Floor address. Sub-register access will be handled by byte-enables
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addr_q <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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addr_q <= {HADDR[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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operation_q <= HWRITE ? WRITE : READ;
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end
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end
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@ -121,7 +121,7 @@ module srdl2sv_amba3ahblite
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begin
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if (HREADYOUT)
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// Floor address. Sub-register access will be handled by byte-enables
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addr_q <= {HADDR[BUS_BITS-1:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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addr_q <= {HADDR[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
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end
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endcase
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end
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@ -237,10 +237,10 @@ module srdl2sv_amba3ahblite
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/***
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* Determine the number of active bytes
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***/
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logic [3:0] HSIZE_bitfielded;
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logic [3:0] b2r_byte_en_next;
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logic b2r_w_vld_next;
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logic b2r_r_vld_next;
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logic [BUS_BYTES-1:0] HSIZE_bitfielded;
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logic [BUS_BYTES-1:0] b2r_byte_en_next;
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logic b2r_w_vld_next;
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logic b2r_r_vld_next;
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always_comb
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begin
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@ -13,7 +13,7 @@ module_instantiation:
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*******************************************************************/
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srdl2sv_amba3ahblite
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#(.FLOP_REGISTER_IF (0),
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.BUS_BITS (32))
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.BUS_BITS ({bus_width}))
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srdl2sv_amba3ahblite_inst
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(// Outputs to internal logic
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.b2r,
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@ -56,7 +56,7 @@ module_instantiation:
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- name: 'HTRANS'
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signal_type: '[1:0]'
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- name: 'HWDATA'
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signal_type: '[31:0]'
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signal_type: '[{bus_width}-1:0]'
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- name: 'HSEL'
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signal_type: ''
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output_ports:
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@ -65,4 +65,4 @@ module_instantiation:
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- name: 'HRESP'
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signal_type: ''
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- name: 'HRDATA'
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signal_type: '[31:0]'
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signal_type: '[{bus_width}-1:0]'
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@ -1,17 +1,17 @@
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package srdl2sv_if_pkg;
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typedef struct packed { // .Verilator does not support unpacked structs in packages
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logic [31:0] addr;
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logic [31:0] data;
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typedef struct packed {{ // .Verilator does not support unpacked structs in packages
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logic [{addrwidth}:0] addr;
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logic [{regwidth_bit}:0] data;
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logic w_vld;
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logic r_vld;
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logic [ 3:0] byte_en;
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} b2r_t;
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logic [ {regwidth_byte}:0] byte_en;
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}} b2r_t;
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typedef struct packed { // .Verilator does not support unpacked structs in packages
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logic [31:0] data;
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typedef struct packed {{ // .Verilator does not support unpacked structs in packages
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logic [{regwidth_bit}:0] data;
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logic rdy;
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logic err;
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} r2b_t;
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}} r2b_t;
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endpackage
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@ -97,7 +97,12 @@ if __name__ == "__main__":
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out_if_file = "{}/srdl2sv_if_pkg.sv".format(config['output_dir'])
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with open(out_if_file, 'w') as file:
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print(widget_if_rtl,file=file)
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widget_if_rtl_parsed = widget_if_rtl.format(
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regwidth_bit = addrmap.get_regwidth() - 1,
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regwidth_byte = int(addrmap.get_regwidth() / 8) - 1,
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addrwidth = config['addrwidth'] - 1)
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print(widget_if_rtl_parsed,file=file)
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logger.info("Copied 'srdl2sv_if_pkg.sv")
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@ -1,5 +1,6 @@
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addrmap simple_rw_reg {
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reg {
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regwidth = 64;
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field {sw=rw; hw=rw;} f1 [15:0];
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field {sw=rw; hw=rw;} f2 [31:16];
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} register_0 [2];
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