Add support for inline-comments
It is possible to enable them for: - fields - registers - regfiles - addrmaps
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16d1774cd2
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GPG Key ID:
186A8AD440942BAF
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@ -85,6 +85,13 @@ class CliArguments():
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help="Define how many tabs or spaces will be contained\
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in one level of indentation. (default: %(default)s)")
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self.parser.add_argument(
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"-i",
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"--include_desc",
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type=int,
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default=0,
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help="Include descriptions of addrmaps (+8), regfiles (+4), registers \
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(+2), and fields (+1) in RTL. This is a bitfield.")
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self.parser.add_argument(
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"IN_RDL",
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@ -97,12 +104,12 @@ class CliArguments():
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# Create dictionary to save config in
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config = dict()
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config['list_args'] = list()
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config['list_args'] = []
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# Save input file and output directory to dump everything in
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config['input_file'] = args.IN_RDL
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config['output_dir'] = args.out_dir
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config['list_args'].append('Ouput Directory : {}'.format(config['output_dir']))
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config['list_args'].append(f"Ouput Directory : {config['output_dir']}")
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# Create output directory
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try:
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@ -113,8 +120,8 @@ class CliArguments():
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# Map logging level string to integers
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config['stream_log_level'] = logging_map[args.stream_log_level]
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config['file_log_level'] = logging_map[args.file_log_level]
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config['list_args'].append('Stream Log Level : {}'.format(args.stream_log_level))
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config['list_args'].append('File Log Level : {}'.format(args.file_log_level))
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config['list_args'].append(f"Stream Log Level : {args.stream_log_level}")
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config['list_args'].append(f"File Log Level : {args.file_log_level}")
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# Determine paths to be passed to systemrdl-compiler to search
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# for include files.
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@ -131,26 +138,35 @@ class CliArguments():
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# Determine name of file to hold logs
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ts = time.strftime('%Y%m%d_%H%M%S', config['ts'])
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config['file_log_location'] = "/".join([config['output_dir'], "srdl2sv_{}.log".format(ts)])
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config['file_log_location'] = "/".join([config['output_dir'], f"srdl2sv_{ts}.log"])
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# Tab style
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config['real_tabs'] = args.real_tabs
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config['tab_width'] = args.tab_width
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config['list_args'].append('Use Real Tabs : {}'.format(config['real_tabs']))
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config['list_args'].append('Tab Width : {}'.format(config['tab_width']))
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config['list_args'].append(f"Use Real Tabs : {config['real_tabs']}")
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config['list_args'].append(f"Tab Width : {config['tab_width']}")
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# Set enums
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config['enums'] = not args.disable_enums
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config['list_args'].append('Enums Enabled : {}'.format(config['enums']))
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config['list_args'].append(f"Enums Enabled : {config['enums']}")
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# Set bus
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config['bus'] = args.bus
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config['list_args'].append('Register Bus Type: {}'.format(config['bus']))
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config['list_args'].append(f"Register Bus Type: {config['bus']}")
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if args.bus == 'amba3ahblite':
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config['addrwidth'] = 32
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# Set location where descirptions shall be set
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# Comparison to 1 to get a Python bool
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config['descriptions'] = {}
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config['descriptions']['addrmap'] = (args.include_desc >> 3) & 1 == 1
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config['descriptions']['regfile'] = (args.include_desc >> 2) & 1 == 1
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config['descriptions']['field'] = (args.include_desc >> 1) & 1 == 1
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config['descriptions']['register'] = (args.include_desc >> 0) & 1 == 1
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config['list_args'].append(f"Descriptions : {config['descriptions']}")
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# Set version
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config['version'] = '0.01'
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@ -196,6 +196,9 @@ class AddrMap(Component):
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inputs = '\n'.join(input_ports_rtl),
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outputs = '\n'.join(output_ports_rtl)))
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# Add description, if applicable
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self.rtl_header.append(self.get_description())
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# Add wire/register instantiations
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self.__add_signal_instantiation()
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@ -390,3 +393,13 @@ class AddrMap(Component):
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def get_regwidth(self) -> int:
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return self.regwidth
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def get_description(self):
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if self.config['descriptions']['addrmap']:
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if desc := self.obj.get_property('desc'):
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return self.process_yaml(
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AddrMap.templ_dict['addrmap_desc'],
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{'desc': desc},
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)
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return ''
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@ -318,3 +318,4 @@ class Component():
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path_underscored = path.replace('.', '__')
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return (owning_addrmap, full_path, path, path_underscored)
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@ -41,6 +41,9 @@ class Field(Component):
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# Print a summary
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self.rtl_header.append(self.summary())
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# Add description
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self.rtl_header.append(self.get_description())
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# HW Access can be handled in __init__ function but SW access
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# must be handled in a seperate method that can be called
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# seperately in case of alias registers
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@ -1369,3 +1372,13 @@ class Field(Component):
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self.logger.error("It's not possible to combine the sticky(bit) "\
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"property with the counter property. The counter property "\
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"will be ignored.")
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def get_description(self):
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if self.config['descriptions']['field']:
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if desc := self.obj.get_property('desc'):
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return self.process_yaml(
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Field.templ_dict['field_desc'],
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{'desc': desc},
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)
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return ''
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@ -103,6 +103,12 @@ class RegFile(Component):
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self.rtl_header.append("")
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self.rtl_header.append("generate")
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# Add description, if applicable
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self.rtl_header = [
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self.get_description(),
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*self.rtl_header
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]
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# Create comment and provide user information about register he/she
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# is looking at.
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self.rtl_header = [
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@ -261,3 +267,12 @@ class RegFile(Component):
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def get_regwidth(self) -> int:
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return self.regwidth
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def get_description(self):
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if self.config['descriptions']['regfile']:
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if desc := self.obj.get_property('desc'):
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return self.process_yaml(
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RegFile.templ_dict['regfile_desc'],
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{'desc': desc},
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)
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return ''
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@ -93,6 +93,12 @@ class Register(Component):
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# regfile which create a generate
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self.__add_signal_instantiations()
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# Add description, if applicable
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self.rtl_header = [
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self.get_description(),
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*self.rtl_header
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]
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# Create comment and provide user information about register he/she is looking at
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self.rtl_header = [
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Register.templ_dict['reg_comment'].format(
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@ -567,3 +573,12 @@ class Register(Component):
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def get_regwidth(self) -> int:
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return self.obj.get_property('regwidth')
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def get_description(self):
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if self.config['descriptions']['register']:
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if desc := self.obj.get_property('desc'):
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return self.process_yaml(
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Register.templ_dict['reg_desc'],
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{'desc': desc},
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)
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return ''
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@ -58,6 +58,14 @@ header: |-
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************/
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addrmap_desc:
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rtl: |-
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/*******************************************************************
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/**ADDRMAP DESCRIPTION**********************************************
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/*******************************************************************
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{desc}
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/*******************************************************************/
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module_declaration:
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rtl: |-
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@ -171,6 +171,12 @@ field_comment:
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// flags : {misc_flags}
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// external : {external}
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//-----------------------------------------------
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field_desc:
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rtl: |-
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/********************DESCRIPTION*****************
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{desc}
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/************************************************/
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combo_operation_comment:
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rtl: |-
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@ -8,6 +8,12 @@ regfile_comment:
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* DEPTHS (per dimension): {depth}
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*******************************************************************
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*******************************************************************/
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regfile_desc:
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rtl: |-
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/**REGISTER DESCRIPTION*********************************************
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{desc}
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/*******************************************************************/
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generate_for_start:
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rtl: |-
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for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
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@ -53,12 +53,18 @@ rw_wire_assign_any_alias:
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reg_comment: |-
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/*******************************************************************
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*******************************************************************
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* REGISTER : {name}
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* DIMENSION : {dimensions}
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* DEPTHS (per dimension): {depth}
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*******************************************************************
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*******************************************************************/
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/*******************************************************************
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/* REGISTER : {name}
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/* DIMENSION : {dimensions}
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/* DEPTHS (per dimension): {depth}
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/*******************************************************************
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/*******************************************************************/
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reg_desc:
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rtl: |-
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/**REGISTER DESCRIPTION*********************************************
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{desc}
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/*******************************************************************/
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generate_for_start: |-
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for ({iterator} = 0; {iterator} < {limit}; {iterator}++)
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begin
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