Closes #8: Certain fields shall be implemented as wires or constants
The software now detects whether a field shall be implemented with flops, with wires, or as a constant. Everything should now follow Table 12 and Section 9.5.1 of the SystemRDL 2.0 LRM.
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GPG Key ID:
186A8AD440942BAF
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@ -3,6 +3,7 @@ import math
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import importlib.resources as pkg_resources
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import sys
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from typing import Optional
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from enum import Enum
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import yaml
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from systemrdl.node import FieldNode, SignalNode
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@ -13,6 +14,11 @@ from systemrdl.rdltypes import PrecedenceType, AccessType, OnReadType, OnWriteTy
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from srdl2sv.components.component import Component, TypeDef
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from srdl2sv.components import templates
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class StorageType(Enum):
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FLOPS = 0
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WIRE = 1
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CONST = 2
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class Field(Component):
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# Save YAML template as class variable
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templ_dict = yaml.load(
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@ -36,6 +42,9 @@ class Field(Component):
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# Save and/or process important variables
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self.__init_variables(obj)
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# Determine whether it is a wire, flops, or a wire
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self.__init_storage_type()
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# Determine field types
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self.__init_fieldtype()
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@ -54,18 +63,25 @@ class Field(Component):
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# HW Access can be handled in __init__ function but SW access
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# must be handled in a seperate method that can be called
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# seperately in case of alias registers
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if not self.config['external']:
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if self.config['external']:
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pass
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elif self.storage_type is not StorageType.FLOPS:
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self.__add_wire_const()
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self.__add_hw_rd_access()
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self.add_sw_access(obj)
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else:
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self.__add_always_ff()
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# Only add normal hardware access if field is not an interrupt field
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if not self.__add_interrupt():
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self.__add_hw_access()
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self.__add_hw_wr_access()
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self.__add_hw_rd_access()
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self.__add_combo()
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self.__add_swmod_swacc()
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self.__add_counter()
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self.add_sw_access(obj)
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self.add_sw_access(obj)
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def add_sw_access(self, obj, alias = False):
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access_rtl = {}
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@ -871,7 +887,23 @@ class Field(Component):
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return self.properties['intr']
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def __add_hw_access(self):
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def __add_wire_const(self):
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field_templ = 'hw_wire' if self.storage_type is StorageType.WIRE else 'hw_const'
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self.access_rtl['hw_write'] = ([
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self._process_yaml(
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Field.templ_dict[field_templ],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'field_type': self.field_type,
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'width': self.obj.width,
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'const': self.rst['value'],
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}
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)
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],
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True)
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def __add_hw_wr_access(self):
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# Mutually exclusive. systemrdl-compiler performs check for this
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enable_mask_negl = ''
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enable_mask = False
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@ -1012,6 +1044,7 @@ class Field(Component):
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else:
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self.access_rtl['hw_setclr'] = ([], False)
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def __add_hw_rd_access(self):
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# Hookup flop to output port in case register is readable by hardware
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if self.obj.get_property('hw') in (AccessType.rw, AccessType.r):
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# Connect flops to output port
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@ -1131,12 +1164,13 @@ class Field(Component):
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# Chain access RTL to the rest of the RTL
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self.rtl_header = [*self.rtl_header, *order_list_rtl]
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self.rtl_header.append(
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self._process_yaml(
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Field.templ_dict['end_field_ff'],
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{'path': self.path_underscored}
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if self.storage_type is StorageType.FLOPS:
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self.rtl_header.append(
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self._process_yaml(
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Field.templ_dict['end_field_ff'],
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{'path': self.path_underscored}
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)
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)
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)
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def __add_combo(self):
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operations = []
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@ -1267,24 +1301,43 @@ class Field(Component):
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if self.rst['name']:
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self.resets.add(self.rst['name'])
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elif obj.get_property("reset") is not None:
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self.logger.warning("Field has a reset value, but no reset "\
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"signal was defined and connected to the "\
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"field. Note that explicit connecting this "\
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"is not required if a field_reset was defined.")
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# Value of reset must always be determined on field level
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# Don't use 'not obj.get_property("reset"), since the value
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# could (and will often be) be '0'
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self.rst['value'] = \
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'\'x' if obj.get_property("reset") == None else\
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obj.get_property('reset')
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'x' if obj.get_property("reset") is None else\
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obj.get_property('reset')
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# Define dict that holds all RTL
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self.access_rtl = {}
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self.access_rtl['else'] = (["else"], False)
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self.access_rtl[''] = ([''], False)
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def __init_storage_type(self):
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# It is not required to check for illegal conditions because the
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# compiler will take care of this
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hw_prop = self.obj.get_property('hw')
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sw_prop = self.obj.get_property('sw')
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# Check the storage type, according to Table 12 of the SystemRDL 2.0 LRM
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if hw_prop is AccessType.r and sw_prop is AccessType.r:
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# hw=r/sw=r --> Constant
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self.storage_type = StorageType.CONST
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elif hw_prop is AccessType.na and sw_prop is AccessType.r:
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# hw=na/sw=r --> Constant
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self.storage_type = StorageType.CONST
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elif hw_prop is AccessType.w and sw_prop is AccessType.r \
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and self.obj.get_property("reset") is None \
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and not self.we_or_wel:
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# If hw=w/sw=r AND no reset or we/wel is defined, a simple wire is implemented.
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# This isn't clear from Table 12, but '9.5.1 Semantics' describes this
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self.storage_type = StorageType.WIRE
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else:
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self.storage_type = StorageType.FLOPS
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self.logger.debug("Storage type of field detected as '%s'", self.storage_type)
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def __summary(self):
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# Additional flags that are set
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# Use list, rather than set, to ensure the order stays the same
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@ -1315,7 +1368,9 @@ class Field(Component):
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external = self.config['external'],
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lsb = self.obj.lsb,
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msb = self.obj.msb,
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path_wo_field = self.path_wo_field)
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path_wo_field = self.path_wo_field,
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storage_type = self.storage_type,
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)
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def __add_always_ff(self):
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# Handle always_ff
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@ -1340,7 +1395,9 @@ class Field(Component):
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'rst_negl': "!" if self.rst['active'] == "active_low" else "",
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'rst_value': self.rst['value'],
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'genvars': self.genvars_str,
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'field_type': self.field_type}
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'field_type': self.field_type,
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'width': self.obj.width,
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}
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)
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)
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@ -1374,6 +1431,17 @@ class Field(Component):
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"property with the counter property. The counter property "\
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"will be ignored.")
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# If there a reset value is defined but no reset value, throw a warning
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# This is not true in case of a constant
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if not self.rst['name'] \
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and self.obj.get_property("reset") is not None \
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and self.storage_type is StorageType.FLOPS:
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self.logger.warning("Field has a reset value, but no reset "\
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"signal was defined and connected to the "\
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"field. Note that explicit connecting this "\
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"is not required if a field_reset was defined.")
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@staticmethod
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def __process_reset_signal(reset_signal):
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rst = {}
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@ -1395,7 +1463,7 @@ class Field(Component):
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rst['async'] = False
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rst['name'] = None
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rst['edge'] = None
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rst['value'] = "'x"
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rst['value'] = "x"
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rst['active'] = "-"
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rst['type'] = "-"
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@ -9,7 +9,7 @@ rst_field_assign:
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rtl: |-
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if ({rst_negl}{rst_name})
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begin
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{path}_q{genvars} <= {rst_value};
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{path}_q{genvars} <= {width}'d{rst_value};
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end
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else
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signals:
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@ -108,6 +108,25 @@ hw_access_counter:
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signal_type: 'logic'
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- name: '{path}_next'
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signal_type: '{field_type}'
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hw_const:
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rtl: |-
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// Field is defined as a constant.
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assign {path}_q{genvars} = {width}'d{const};
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signals:
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- name: '{path}_q'
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signal_type: '{field_type}'
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hw_wire:
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rtl: |-
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// Field is a simple wire.
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// To generate a flop either add the we/wel property, add
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// a reset, or change the sw/hw access properties
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assign {path}_q{genvars} = {path}_in{genvars};
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signals:
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- name: '{path}_q'
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signal_type: '{field_type}'
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input_ports:
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- name: '{path}_in'
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signal_type: '{field_type}'
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end_field_ff:
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rtl: |-
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end // of {path}'s always_ff
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@ -164,12 +183,13 @@ field_comment:
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rtl: |-
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//-----------------FIELD SUMMARY-----------------
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// name : {name} ({path_wo_field}[{msb}:{lsb}])
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// access : hw = {hw_access} {hw_precedence}
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// sw = {sw_access} {sw_precedence}
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// reset : {rst_active} / {rst_type}
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// flags : {misc_flags}
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// external : {external}
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// name : {name} ({path_wo_field}[{msb}:{lsb}])
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// access : hw = {hw_access} {hw_precedence}
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// sw = {sw_access} {sw_precedence}
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// reset : {rst_active} / {rst_type}
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// flags : {misc_flags}
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// external : {external}
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// storage type : {storage_type}
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//-----------------------------------------------
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field_desc:
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rtl: |-
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