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Update srdl2sv examples with widget<->interface changes

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These changes were introduced in 85f7808 in order to close #4.
This commit is contained in:
Dennis Potter 2021-10-27 23:33:42 -07:00
parent 85f7808362
commit e6cfec9c32
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
8 changed files with 409 additions and 402 deletions
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442
examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv
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File diff suppressed because it is too large Load Diff

65
examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_amba3ahblite.sv
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@ -23,20 +23,12 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
module srdl2sv_amba3ahblite
import srdl2sv_if_pkg::*;
#(
module srdl2sv_amba3ahblite #(
parameter bit FLOP_REGISTER_IF = 0,
parameter BUS_BITS = 32,
parameter NO_BYTE_ENABLE = 0
)
(
// Outputs to internal logic
output b2r_t b2r,
// Inputs from internal logic
input r2b_t r2b,
// Bus protocol
input HCLK,
input HRESETn,
@ -50,7 +42,10 @@ module srdl2sv_amba3ahblite
output logic HREADYOUT,
output logic HRESP,
output logic [BUS_BITS-1:0] HRDATA
output logic [BUS_BITS-1:0] HRDATA,
// Interface to internal logic
srdl2sv_widget_if.widget widget_if
);
localparam BUS_BYTES = BUS_BITS/8;
@ -145,7 +140,7 @@ module srdl2sv_amba3ahblite
// When reading back, the data of the bit that was accessed over the bus
// should be at byte 0 of the HRDATA bus and bits that were not accessed
// should be masked with 0s.
HRDATA_temp = r2b.data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
HRDATA_temp = widget_if.r_data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
for (int i = 0; i < BUS_BYTES; i++)
if (i < (1 << HSIZE_q))
@ -153,8 +148,8 @@ module srdl2sv_amba3ahblite
else
HRDATA[8*(i+1)-1 -: 8] = 8'b0;
b2r_w_vld_next = 0;
b2r_r_vld_next = 0;
widget_if_w_vld_next = 0;
widget_if_r_vld_next = 0;
fsm_next = fsm_q;
case (fsm_q)
@ -175,11 +170,11 @@ module srdl2sv_amba3ahblite
end
FSM_TRANS:
begin
HREADYOUT = r2b.rdy;
b2r_w_vld_next = operation_q == WRITE;
b2r_r_vld_next = operation_q == READ;
HREADYOUT = widget_if.rdy;
widget_if_w_vld_next = operation_q == WRITE;
widget_if_r_vld_next = operation_q == READ;
if (r2b.err && r2b.rdy)
if (widget_if.err && widget_if.rdy)
begin
fsm_next = FSM_ERR_0;
end
@ -201,7 +196,7 @@ module srdl2sv_amba3ahblite
else if (HTRANS == IDLE)
begin
// All done, wrapping things up!
fsm_next = r2b.rdy ? FSM_IDLE : FSM_TRANS;
fsm_next = widget_if.rdy ? FSM_IDLE : FSM_TRANS;
end
end
FSM_ERR_0:
@ -253,14 +248,14 @@ module srdl2sv_amba3ahblite
* Determine the number of active bytes
***/
logic [BUS_BYTES-1:0] HSIZE_bitfielded;
logic [BUS_BYTES-1:0] b2r_byte_en_next;
logic b2r_w_vld_next;
logic b2r_r_vld_next;
logic [BUS_BYTES-1:0] widget_if_byte_en_next;
logic widget_if_w_vld_next;
logic widget_if_r_vld_next;
generate
if (NO_BYTE_ENABLE)
begin
assign b2r_byte_en_next = {BUS_BYTES{1'b1}};
assign widget_if_byte_en_next = {BUS_BYTES{1'b1}};
end
else
begin
@ -270,7 +265,7 @@ module srdl2sv_amba3ahblite
HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
// Shift if not the full bus is accessed
b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
widget_if_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
end
end
endgenerate
@ -284,29 +279,29 @@ module srdl2sv_amba3ahblite
always_ff @ (posedge HCLK or negedge HRESETn)
if (!HRESETn)
begin
b2r.w_vld <= 1'b0;
b2r.r_vld <= 1'b0;
widget_if.w_vld <= 1'b0;
widget_if.r_vld <= 1'b0;
end
else
begin
b2r.w_vld <= b2r_w_vld_next;
b2r.r_vld <= b2r_r_vld_next;
widget_if.w_vld <= widget_if_w_vld_next;
widget_if.r_vld <= widget_if_r_vld_next;
end
always_ff @ (posedge HCLK)
begin
b2r.addr <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
b2r.data <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
b2r.byte_en <= b2r_byte_en_next;
widget_if.addr <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
widget_if.w_data <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
widget_if.byte_en <= widget_if_byte_en_next;
end
end
else
begin
assign b2r.w_vld = b2r_w_vld_next;
assign b2r.r_vld = b2r_r_vld_next;
assign b2r.addr = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
assign b2r.data = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
assign b2r.byte_en = b2r_byte_en_next;
assign widget_if.w_vld = widget_if_w_vld_next;
assign widget_if.r_vld = widget_if_r_vld_next;
assign widget_if.addr = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
assign widget_if.w_data = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
assign widget_if.byte_en = widget_if_byte_en_next;
end
endgenerate

18
examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_if_pkg.sv
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@ -1,18 +0,0 @@
package srdl2sv_if_pkg;
typedef struct packed { // .Verilator does not support unpacked structs in packages
logic [31:0] addr;
logic [31:0] data;
logic w_vld;
logic r_vld;
logic [ 3:0] byte_en;
} b2r_t;
typedef struct packed { // .Verilator does not support unpacked structs in packages
logic [31:0] data;
logic rdy;
logic err;
} r2b_t;
endpackage

30
examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_widget_if.sv Normal file
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@ -0,0 +1,30 @@
interface srdl2sv_widget_if #(
parameter ADDR_W = 32,
parameter DATA_W = 32
);
localparam DATA_BYTES = DATA_W >> 3;
logic [ADDR_W-1:0] addr;
logic [DATA_W-1:0] w_data;
logic w_vld;
logic r_vld;
logic [DATA_BYTES-1:0] byte_en;
logic [DATA_W-1:0] r_data;
logic rdy;
logic err;
modport widget (
output addr,
output w_data,
output w_vld,
output r_vld,
output byte_en,
input r_data,
input rdy,
input err
);
endinterface

143
examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv
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@ -20,8 +20,8 @@
*
* Generation information:
* - User: : dpotter
* - Time : October 20 2021 23:49:07
* - Path : /home/dpotter/srdl2sv_second_repo/examples/simple_rw_reg
* - Time : October 27 2021 23:33:01
* - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg
* - RDL file : ['simple_rw_reg.rdl']
* - Hostname : ArchXPS
*
@ -31,11 +31,12 @@
* Commandline arguments to srdl2sv:
* - Ouput Directory : ./srdl2sv_out
* - Stream Log Level : INFO
* - File Log Level : INFO
* - File Log Level : NONE
* - Use Real Tabs : False
* - Tab Width : 4
* - Enums Enabled : True
* - Register Bus Type: amba3ahblite
* - Address width : 32
* - Byte enables : True
* - Descriptions : {'AddrMap': False, 'RegFile': False, 'Memory': False, 'Register': False, 'Field': False}
*
@ -65,7 +66,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
****************************************************************/
module simple_rw_reg
import srdl2sv_if_pkg::*;
(
// Resets
@ -107,15 +108,14 @@ module simple_rw_reg
// Internal signals
b2r_t b2r;
r2b_t r2b;
srdl2sv_widget_if #(.ADDR_W (32), .DATA_W(32)) widget_if;
/*******************************************************************
* AMBA 3 AHB Lite Widget
* ======================
* Naming conventions
* - r2b.* -> Signals from registers to bus
* - b2r.* -> Signals from bus to registers
* - widget_if -> SystemVerilog interface to between widgets
* and the internal srdl2sv registers.
* - H* -> Signals as defined in AMBA3 AHB Lite
* specification
* - clk -> Clock that drives registers and the bus
@ -125,13 +125,7 @@ srdl2sv_amba3ahblite
.BUS_BITS (32),
.NO_BYTE_ENABLE (0))
srdl2sv_amba3ahblite_inst
(// Outputs to internal logic
.b2r,
// Inputs from internal logic
.r2b,
// Bus protocol
(// Bus protocol
.HRESETn,
.HCLK (clk),
.HADDR,
@ -144,7 +138,10 @@ srdl2sv_amba3ahblite_inst
.HREADYOUT,
.HRESP,
.HRDATA);
.HRDATA,
// Interface to internal logic
.widget_if);
genvar gv_a, gv_b;
@ -167,8 +164,8 @@ logic [15:0] register_1d__f2_q ;
// Register-activation for 'register_1d'
assign register_1d_active = b2r.addr == 0;
assign register_1d_sw_wr = register_1d_active && b2r.w_vld;
assign register_1d_active = widget_if.addr == 0;
assign register_1d_sw_wr = register_1d_active && widget_if.w_vld;
//-----------------FIELD SUMMARY-----------------
// name : f1 (register_1d[15:0])
@ -183,10 +180,10 @@ always_ff @(posedge clk)
begin
if (register_1d_sw_wr)
begin
if (b2r.byte_en[0])
register_1d__f1_q[7:0] <= b2r.data[7:0];
if (b2r.byte_en[1])
register_1d__f1_q[15:8] <= b2r.data[15:8];
if (widget_if.byte_en[0])
register_1d__f1_q[7:0] <= widget_if.w_data[7:0];
if (widget_if.byte_en[1])
register_1d__f1_q[15:8] <= widget_if.w_data[15:8];
end
else
if (register_1d__f1_hw_wr)
@ -211,10 +208,10 @@ always_ff @(posedge clk)
begin
if (register_1d_sw_wr)
begin
if (b2r.byte_en[2])
register_1d__f2_q[7:0] <= b2r.data[23:16];
if (b2r.byte_en[3])
register_1d__f2_q[15:8] <= b2r.data[31:24];
if (widget_if.byte_en[2])
register_1d__f2_q[7:0] <= widget_if.w_data[23:16];
if (widget_if.byte_en[3])
register_1d__f2_q[15:8] <= widget_if.w_data[31:24];
end
else
if (register_1d__f2_hw_wr)
@ -239,7 +236,7 @@ assign register_1d_rdy_mux_in = 1'b1;
// Return an error if *no* read and *no* write was succesful. If some bits
// cannot be read/written but others are succesful, don't return and error
// Hence, as long as one action can be succesful, no error will be returned.
assign register_1d_err_mux_in = !((b2r.r_vld && (b2r.byte_en[0] || b2r.byte_en[1] || b2r.byte_en[2] || b2r.byte_en[3])) || (b2r.w_vld && (b2r.byte_en[0] || b2r.byte_en[1] || b2r.byte_en[2] || b2r.byte_en[3])));
assign register_1d_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])));
/*******************************************************************
/*******************************************************************
@ -262,8 +259,8 @@ for (gv_a = 0; gv_a < 2; gv_a++)
begin
// Register-activation for 'register_2d'
assign register_2d_active[gv_a] = b2r.addr == 4+(gv_a*4);
assign register_2d_sw_wr[gv_a] = register_2d_active[gv_a] && b2r.w_vld;
assign register_2d_active[gv_a] = widget_if.addr == 4+(gv_a*4);
assign register_2d_sw_wr[gv_a] = register_2d_active[gv_a] && widget_if.w_vld;
//-----------------FIELD SUMMARY-----------------
// name : f1 (register_2d[15:0])
@ -278,10 +275,10 @@ begin
begin
if (register_2d_sw_wr[gv_a])
begin
if (b2r.byte_en[0])
register_2d__f1_q[gv_a][7:0] <= b2r.data[7:0];
if (b2r.byte_en[1])
register_2d__f1_q[gv_a][15:8] <= b2r.data[15:8];
if (widget_if.byte_en[0])
register_2d__f1_q[gv_a][7:0] <= widget_if.w_data[7:0];
if (widget_if.byte_en[1])
register_2d__f1_q[gv_a][15:8] <= widget_if.w_data[15:8];
end
else
if (register_2d__f1_hw_wr[gv_a])
@ -306,10 +303,10 @@ begin
begin
if (register_2d_sw_wr[gv_a])
begin
if (b2r.byte_en[2])
register_2d__f2_q[gv_a][7:0] <= b2r.data[23:16];
if (b2r.byte_en[3])
register_2d__f2_q[gv_a][15:8] <= b2r.data[31:24];
if (widget_if.byte_en[2])
register_2d__f2_q[gv_a][7:0] <= widget_if.w_data[23:16];
if (widget_if.byte_en[3])
register_2d__f2_q[gv_a][15:8] <= widget_if.w_data[31:24];
end
else
if (register_2d__f2_hw_wr[gv_a])
@ -334,7 +331,7 @@ begin
// Return an error if *no* read and *no* write was succesful. If some bits
// cannot be read/written but others are succesful, don't return and error
// Hence, as long as one action can be succesful, no error will be returned.
assign register_2d_err_mux_in[gv_a] = !((b2r.r_vld && (b2r.byte_en[0] || b2r.byte_en[1] || b2r.byte_en[2] || b2r.byte_en[3])) || (b2r.w_vld && (b2r.byte_en[0] || b2r.byte_en[1] || b2r.byte_en[2] || b2r.byte_en[3])));
assign register_2d_err_mux_in[gv_a] = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])));
end // of for loop with iterator gv_a
endgenerate
@ -363,8 +360,8 @@ begin
begin
// Register-activation for 'register_3d'
assign register_3d_active[gv_a][gv_b] = b2r.addr == 12+(gv_a*8+gv_b*4);
assign register_3d_sw_wr[gv_a][gv_b] = register_3d_active[gv_a][gv_b] && b2r.w_vld;
assign register_3d_active[gv_a][gv_b] = widget_if.addr == 12+(gv_a*8+gv_b*4);
assign register_3d_sw_wr[gv_a][gv_b] = register_3d_active[gv_a][gv_b] && widget_if.w_vld;
//-----------------FIELD SUMMARY-----------------
// name : f1 (register_3d[15:0])
@ -379,10 +376,10 @@ begin
begin
if (register_3d_sw_wr[gv_a][gv_b])
begin
if (b2r.byte_en[0])
register_3d__f1_q[gv_a][gv_b][7:0] <= b2r.data[7:0];
if (b2r.byte_en[1])
register_3d__f1_q[gv_a][gv_b][15:8] <= b2r.data[15:8];
if (widget_if.byte_en[0])
register_3d__f1_q[gv_a][gv_b][7:0] <= widget_if.w_data[7:0];
if (widget_if.byte_en[1])
register_3d__f1_q[gv_a][gv_b][15:8] <= widget_if.w_data[15:8];
end
else
if (register_3d__f1_hw_wr[gv_a][gv_b])
@ -407,10 +404,10 @@ begin
begin
if (register_3d_sw_wr[gv_a][gv_b])
begin
if (b2r.byte_en[2])
register_3d__f2_q[gv_a][gv_b][7:0] <= b2r.data[23:16];
if (b2r.byte_en[3])
register_3d__f2_q[gv_a][gv_b][15:8] <= b2r.data[31:24];
if (widget_if.byte_en[2])
register_3d__f2_q[gv_a][gv_b][7:0] <= widget_if.w_data[23:16];
if (widget_if.byte_en[3])
register_3d__f2_q[gv_a][gv_b][15:8] <= widget_if.w_data[31:24];
end
else
if (register_3d__f2_hw_wr[gv_a][gv_b])
@ -435,7 +432,7 @@ begin
// Return an error if *no* read and *no* write was succesful. If some bits
// cannot be read/written but others are succesful, don't return and error
// Hence, as long as one action can be succesful, no error will be returned.
assign register_3d_err_mux_in[gv_a][gv_b] = !((b2r.r_vld && (b2r.byte_en[0] || b2r.byte_en[1] || b2r.byte_en[2] || b2r.byte_en[3])) || (b2r.w_vld && (b2r.byte_en[0] || b2r.byte_en[1] || b2r.byte_en[2] || b2r.byte_en[3])));
assign register_3d_err_mux_in[gv_a][gv_b] = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])));
end // of for loop with iterator gv_b
end // of for loop with iterator gv_a
@ -448,52 +445,52 @@ begin
unique case (1'b1)
register_1d_active:
begin
r2b.data = register_1d_data_mux_in;
r2b.err = register_1d_err_mux_in;
r2b.rdy = register_1d_rdy_mux_in;
widget_if.r_data = register_1d_data_mux_in;
widget_if.err = register_1d_err_mux_in;
widget_if.rdy = register_1d_rdy_mux_in;
end
register_2d_active[0]:
begin
r2b.data = register_2d_data_mux_in[0];
r2b.err = register_2d_err_mux_in[0];
r2b.rdy = register_2d_rdy_mux_in[0];
widget_if.r_data = register_2d_data_mux_in[0];
widget_if.err = register_2d_err_mux_in[0];
widget_if.rdy = register_2d_rdy_mux_in[0];
end
register_2d_active[1]:
begin
r2b.data = register_2d_data_mux_in[1];
r2b.err = register_2d_err_mux_in[1];
r2b.rdy = register_2d_rdy_mux_in[1];
widget_if.r_data = register_2d_data_mux_in[1];
widget_if.err = register_2d_err_mux_in[1];
widget_if.rdy = register_2d_rdy_mux_in[1];
end
register_3d_active[0][0]:
begin
r2b.data = register_3d_data_mux_in[0][0];
r2b.err = register_3d_err_mux_in[0][0];
r2b.rdy = register_3d_rdy_mux_in[0][0];
widget_if.r_data = register_3d_data_mux_in[0][0];
widget_if.err = register_3d_err_mux_in[0][0];
widget_if.rdy = register_3d_rdy_mux_in[0][0];
end
register_3d_active[0][1]:
begin
r2b.data = register_3d_data_mux_in[0][1];
r2b.err = register_3d_err_mux_in[0][1];
r2b.rdy = register_3d_rdy_mux_in[0][1];
widget_if.r_data = register_3d_data_mux_in[0][1];
widget_if.err = register_3d_err_mux_in[0][1];
widget_if.rdy = register_3d_rdy_mux_in[0][1];
end
register_3d_active[1][0]:
begin
r2b.data = register_3d_data_mux_in[1][0];
r2b.err = register_3d_err_mux_in[1][0];
r2b.rdy = register_3d_rdy_mux_in[1][0];
widget_if.r_data = register_3d_data_mux_in[1][0];
widget_if.err = register_3d_err_mux_in[1][0];
widget_if.rdy = register_3d_rdy_mux_in[1][0];
end
register_3d_active[1][1]:
begin
r2b.data = register_3d_data_mux_in[1][1];
r2b.err = register_3d_err_mux_in[1][1];
r2b.rdy = register_3d_rdy_mux_in[1][1];
widget_if.r_data = register_3d_data_mux_in[1][1];
widget_if.err = register_3d_err_mux_in[1][1];
widget_if.rdy = register_3d_rdy_mux_in[1][1];
end
default:
begin
// If the address is not found, return an error
r2b.data = 0;
r2b.err = 1;
r2b.rdy = b2r.r_vld || b2r.w_vld;
widget_if.r_data = 0;
widget_if.err = 1;
widget_if.rdy = widget_if.r_vld || widget_if.w_vld;
end
endcase
end

65
examples/simple_rw_reg/srdl2sv_out/srdl2sv_amba3ahblite.sv
View File

@ -23,20 +23,12 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
module srdl2sv_amba3ahblite
import srdl2sv_if_pkg::*;
#(
module srdl2sv_amba3ahblite #(
parameter bit FLOP_REGISTER_IF = 0,
parameter BUS_BITS = 32,
parameter NO_BYTE_ENABLE = 0
)
(
// Outputs to internal logic
output b2r_t b2r,
// Inputs from internal logic
input r2b_t r2b,
// Bus protocol
input HCLK,
input HRESETn,
@ -50,7 +42,10 @@ module srdl2sv_amba3ahblite
output logic HREADYOUT,
output logic HRESP,
output logic [BUS_BITS-1:0] HRDATA
output logic [BUS_BITS-1:0] HRDATA,
// Interface to internal logic
srdl2sv_widget_if.widget widget_if
);
localparam BUS_BYTES = BUS_BITS/8;
@ -145,7 +140,7 @@ module srdl2sv_amba3ahblite
// When reading back, the data of the bit that was accessed over the bus
// should be at byte 0 of the HRDATA bus and bits that were not accessed
// should be masked with 0s.
HRDATA_temp = r2b.data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
HRDATA_temp = widget_if.r_data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
for (int i = 0; i < BUS_BYTES; i++)
if (i < (1 << HSIZE_q))
@ -153,8 +148,8 @@ module srdl2sv_amba3ahblite
else
HRDATA[8*(i+1)-1 -: 8] = 8'b0;
b2r_w_vld_next = 0;
b2r_r_vld_next = 0;
widget_if_w_vld_next = 0;
widget_if_r_vld_next = 0;
fsm_next = fsm_q;
case (fsm_q)
@ -175,11 +170,11 @@ module srdl2sv_amba3ahblite
end
FSM_TRANS:
begin
HREADYOUT = r2b.rdy;
b2r_w_vld_next = operation_q == WRITE;
b2r_r_vld_next = operation_q == READ;
HREADYOUT = widget_if.rdy;
widget_if_w_vld_next = operation_q == WRITE;
widget_if_r_vld_next = operation_q == READ;
if (r2b.err && r2b.rdy)
if (widget_if.err && widget_if.rdy)
begin
fsm_next = FSM_ERR_0;
end
@ -201,7 +196,7 @@ module srdl2sv_amba3ahblite
else if (HTRANS == IDLE)
begin
// All done, wrapping things up!
fsm_next = r2b.rdy ? FSM_IDLE : FSM_TRANS;
fsm_next = widget_if.rdy ? FSM_IDLE : FSM_TRANS;
end
end
FSM_ERR_0:
@ -253,14 +248,14 @@ module srdl2sv_amba3ahblite
* Determine the number of active bytes
***/
logic [BUS_BYTES-1:0] HSIZE_bitfielded;
logic [BUS_BYTES-1:0] b2r_byte_en_next;
logic b2r_w_vld_next;
logic b2r_r_vld_next;
logic [BUS_BYTES-1:0] widget_if_byte_en_next;
logic widget_if_w_vld_next;
logic widget_if_r_vld_next;
generate
if (NO_BYTE_ENABLE)
begin
assign b2r_byte_en_next = {BUS_BYTES{1'b1}};
assign widget_if_byte_en_next = {BUS_BYTES{1'b1}};
end
else
begin
@ -270,7 +265,7 @@ module srdl2sv_amba3ahblite
HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
// Shift if not the full bus is accessed
b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
widget_if_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
end
end
endgenerate
@ -284,29 +279,29 @@ module srdl2sv_amba3ahblite
always_ff @ (posedge HCLK or negedge HRESETn)
if (!HRESETn)
begin
b2r.w_vld <= 1'b0;
b2r.r_vld <= 1'b0;
widget_if.w_vld <= 1'b0;
widget_if.r_vld <= 1'b0;
end
else
begin
b2r.w_vld <= b2r_w_vld_next;
b2r.r_vld <= b2r_r_vld_next;
widget_if.w_vld <= widget_if_w_vld_next;
widget_if.r_vld <= widget_if_r_vld_next;
end
always_ff @ (posedge HCLK)
begin
b2r.addr <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
b2r.data <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
b2r.byte_en <= b2r_byte_en_next;
widget_if.addr <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
widget_if.w_data <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
widget_if.byte_en <= widget_if_byte_en_next;
end
end
else
begin
assign b2r.w_vld = b2r_w_vld_next;
assign b2r.r_vld = b2r_r_vld_next;
assign b2r.addr = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
assign b2r.data = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
assign b2r.byte_en = b2r_byte_en_next;
assign widget_if.w_vld = widget_if_w_vld_next;
assign widget_if.r_vld = widget_if_r_vld_next;
assign widget_if.addr = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
assign widget_if.w_data = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
assign widget_if.byte_en = widget_if_byte_en_next;
end
endgenerate

18
examples/simple_rw_reg/srdl2sv_out/srdl2sv_if_pkg.sv
View File

@ -1,18 +0,0 @@
package srdl2sv_if_pkg;
typedef struct packed { // .Verilator does not support unpacked structs in packages
logic [31:0] addr;
logic [31:0] data;
logic w_vld;
logic r_vld;
logic [ 3:0] byte_en;
} b2r_t;
typedef struct packed { // .Verilator does not support unpacked structs in packages
logic [31:0] data;
logic rdy;
logic err;
} r2b_t;
endpackage

30
examples/simple_rw_reg/srdl2sv_out/srdl2sv_widget_if.sv Normal file
View File

@ -0,0 +1,30 @@
interface srdl2sv_widget_if #(
parameter ADDR_W = 32,
parameter DATA_W = 32
);
localparam DATA_BYTES = DATA_W >> 3;
logic [ADDR_W-1:0] addr;
logic [DATA_W-1:0] w_data;
logic w_vld;
logic r_vld;
logic [DATA_BYTES-1:0] byte_en;
logic [DATA_W-1:0] r_data;
logic rdy;
logic err;
modport widget (
output addr,
output w_data,
output w_vld,
output r_vld,
output byte_en,
input r_data,
input rdy,
input err
);
endinterface