diff --git a/srdl2sv/components/field.py b/srdl2sv/components/field.py index e00b740..539884b 100644 --- a/srdl2sv/components/field.py +++ b/srdl2sv/components/field.py @@ -310,6 +310,7 @@ class Field(Component): Field.templ_dict[str(onwrite)]['rtl'].format( path = self.path_underscored, genvars = self.genvars_str, + width = self.obj.width, path_wo_field = self.path_wo_field ) ) @@ -321,6 +322,7 @@ class Field(Component): path = self.path_underscored, genvars = self.genvars_str, i = i, + width = self.obj.width, msb_bus = str(8*(i+1)-1 if i != self.msbyte else self.obj.msb), bus_w = str(8 if i != self.msbyte else self.obj.width-(8*j)), msb_field = str(8*(j+1)-1 if i != self.msbyte else self.obj.width-1), @@ -350,6 +352,7 @@ class Field(Component): else: access_rtl['sw_read'][0].append( Field.templ_dict[str(onread)]['rtl'].format( + width = self.obj.width, path = self.path_underscored, genvars = self.genvars_str, path_wo_field = self.path_wo_field diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml index 7c05b39..21f82ec 100644 --- a/srdl2sv/components/templates/fields.yaml +++ b/srdl2sv/components/templates/fields.yaml @@ -86,21 +86,21 @@ OnWriteType.wzt: end OnWriteType.wclr: rtl: |- - {path}_q{genvars} <= {{width{{1'b0}}}}; + {path}_q{genvars} <= {{{width}{{1'b0}}}}; OnWriteType.wset: rtl: |- - {path}_q{genvars} <= {{width{{1'b1}}}}; + {path}_q{genvars} <= {{{width}{{1'b1}}}}; OnReadType.rclr: rtl: |- if ({path_wo_field}_sw_rd{genvars}) // rclr property begin - {path}_q{genvars} <= {{width{{1'b0}}}}; + {path}_q{genvars} <= {{{width}{{1'b0}}}}; end OnReadType.rset: rtl: |- if ({path_wo_field}_sw_rd{genvars}) // rset property begin - {path}_q{genvars} <= {{width{{1'b1}}}}; + {path}_q{genvars} <= {{{width}{{1'b1}}}}; end field_comment: