From ed167c05de63861ee63fc5bdeddc37ac796fcc4f Mon Sep 17 00:00:00 2001 From: Dennis Date: Sat, 30 Oct 2021 23:35:38 -0700 Subject: [PATCH] Update AMBA 3 AHB Lite widget in examples with 33c92c8 (issue #9) --- .../srdl2sv_out/hierarchical_regfiles.sv | 4 ++-- .../srdl2sv_out/srdl2sv_amba3ahblite.sv | 15 +++++++++------ .../srdl2sv_out/interrupt_hierarchy.sv | 4 ++-- .../srdl2sv_out/srdl2sv_amba3ahblite.sv | 15 +++++++++------ .../simple_rw_reg/srdl2sv_out/simple_rw_reg.sv | 4 ++-- .../srdl2sv_out/srdl2sv_amba3ahblite.sv | 15 +++++++++------ 6 files changed, 33 insertions(+), 24 deletions(-) diff --git a/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv b/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv index 3cfa91b..9921619 100644 --- a/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv +++ b/examples/hierarchical_regfiles/srdl2sv_out/hierarchical_regfiles.sv @@ -14,13 +14,13 @@ * srdl2sv itself is licensed under GPLv3. * * Maintainer : Dennis Potter - * Report Bugs: https://git.dennispotter.eu/Dennis/srdl2sv/issues + * Report Bugs: https://github.com/Silicon1602/srdl2sv/issues * * ===GENERATION INFORMATION====================================== * * Generation information: * - User: : dpotter - * - Time : October 30 2021 19:38:01 + * - Time : October 30 2021 23:34:40 * - Path : /home/dpotter/srdl2sv/examples/hierarchical_regfiles * - RDL file : ['hierarchical_regfiles.rdl'] * - Hostname : ArchXPS diff --git a/examples/hierarchical_regfiles/srdl2sv_out/srdl2sv_amba3ahblite.sv b/examples/hierarchical_regfiles/srdl2sv_out/srdl2sv_amba3ahblite.sv index 52da8c8..d1598f9 100644 --- a/examples/hierarchical_regfiles/srdl2sv_out/srdl2sv_amba3ahblite.sv +++ b/examples/hierarchical_regfiles/srdl2sv_out/srdl2sv_amba3ahblite.sv @@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #( begin // Defaults HREADYOUT = 1'b1; - HRESP = 1'b0; + HRESP = OKAY; // When reading back, the data of the bit that was accessed over the bus // should be at byte 0 of the HRDATA bus and bits that were not accessed @@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #( widget_if_w_vld_next = operation_q == WRITE; widget_if_r_vld_next = operation_q == READ; - if (widget_if.err && widget_if.rdy) - begin - fsm_next = FSM_ERR_0; - end - else if (HTRANS == BUSY) + if (HTRANS == BUSY) begin // Wait fsm_next = FSM_TRANS; end + else if (widget_if.err && widget_if.rdy) + begin + HREADYOUT = 0; + HRESP = ERROR; + fsm_next = FSM_ERR_1; + end else if (HTRANS == NONSEQ) begin // Another unrelated access is coming @@ -307,3 +309,4 @@ module srdl2sv_amba3ahblite #( endmodule + diff --git a/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv b/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv index 9382edc..7946f6b 100644 --- a/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv +++ b/examples/interrupt_hierarchy/srdl2sv_out/interrupt_hierarchy.sv @@ -14,13 +14,13 @@ * srdl2sv itself is licensed under GPLv3. * * Maintainer : Dennis Potter - * Report Bugs: https://git.dennispotter.eu/Dennis/srdl2sv/issues + * Report Bugs: https://github.com/Silicon1602/srdl2sv/issues * * ===GENERATION INFORMATION====================================== * * Generation information: * - User: : dpotter - * - Time : October 30 2021 19:37:23 + * - Time : October 30 2021 23:34:49 * - Path : /home/dpotter/srdl2sv/examples/interrupt_hierarchy * - RDL file : ['interrupt_hierarchy.rdl'] * - Hostname : ArchXPS diff --git a/examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_amba3ahblite.sv b/examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_amba3ahblite.sv index 52da8c8..d1598f9 100644 --- a/examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_amba3ahblite.sv +++ b/examples/interrupt_hierarchy/srdl2sv_out/srdl2sv_amba3ahblite.sv @@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #( begin // Defaults HREADYOUT = 1'b1; - HRESP = 1'b0; + HRESP = OKAY; // When reading back, the data of the bit that was accessed over the bus // should be at byte 0 of the HRDATA bus and bits that were not accessed @@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #( widget_if_w_vld_next = operation_q == WRITE; widget_if_r_vld_next = operation_q == READ; - if (widget_if.err && widget_if.rdy) - begin - fsm_next = FSM_ERR_0; - end - else if (HTRANS == BUSY) + if (HTRANS == BUSY) begin // Wait fsm_next = FSM_TRANS; end + else if (widget_if.err && widget_if.rdy) + begin + HREADYOUT = 0; + HRESP = ERROR; + fsm_next = FSM_ERR_1; + end else if (HTRANS == NONSEQ) begin // Another unrelated access is coming @@ -307,3 +309,4 @@ module srdl2sv_amba3ahblite #( endmodule + diff --git a/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv b/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv index da22fa3..ccc987f 100644 --- a/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv +++ b/examples/simple_rw_reg/srdl2sv_out/simple_rw_reg.sv @@ -14,13 +14,13 @@ * srdl2sv itself is licensed under GPLv3. * * Maintainer : Dennis Potter - * Report Bugs: https://git.dennispotter.eu/Dennis/srdl2sv/issues + * Report Bugs: https://github.com/Silicon1602/srdl2sv/issues * * ===GENERATION INFORMATION====================================== * * Generation information: * - User: : dpotter - * - Time : October 30 2021 19:37:29 + * - Time : October 30 2021 23:34:53 * - Path : /home/dpotter/srdl2sv/examples/simple_rw_reg * - RDL file : ['simple_rw_reg.rdl'] * - Hostname : ArchXPS diff --git a/examples/simple_rw_reg/srdl2sv_out/srdl2sv_amba3ahblite.sv b/examples/simple_rw_reg/srdl2sv_out/srdl2sv_amba3ahblite.sv index 52da8c8..d1598f9 100644 --- a/examples/simple_rw_reg/srdl2sv_out/srdl2sv_amba3ahblite.sv +++ b/examples/simple_rw_reg/srdl2sv_out/srdl2sv_amba3ahblite.sv @@ -135,7 +135,7 @@ module srdl2sv_amba3ahblite #( begin // Defaults HREADYOUT = 1'b1; - HRESP = 1'b0; + HRESP = OKAY; // When reading back, the data of the bit that was accessed over the bus // should be at byte 0 of the HRDATA bus and bits that were not accessed @@ -174,15 +174,17 @@ module srdl2sv_amba3ahblite #( widget_if_w_vld_next = operation_q == WRITE; widget_if_r_vld_next = operation_q == READ; - if (widget_if.err && widget_if.rdy) - begin - fsm_next = FSM_ERR_0; - end - else if (HTRANS == BUSY) + if (HTRANS == BUSY) begin // Wait fsm_next = FSM_TRANS; end + else if (widget_if.err && widget_if.rdy) + begin + HREADYOUT = 0; + HRESP = ERROR; + fsm_next = FSM_ERR_1; + end else if (HTRANS == NONSEQ) begin // Another unrelated access is coming @@ -307,3 +309,4 @@ module srdl2sv_amba3ahblite #( endmodule +