diff --git a/srdl2sv/components/addrmap.py b/srdl2sv/components/addrmap.py index ae1cf2f..eb5d9c8 100644 --- a/srdl2sv/components/addrmap.py +++ b/srdl2sv/components/addrmap.py @@ -275,7 +275,8 @@ class AddrMap(Component): def __append_genvars(self): - genvars = ', '.join([chr(97+i) for i in range(self.get_max_dim_depth())]) + genvars = ', '.join([''.join(['gv_', chr(97+i)]) + for i in range(self.get_max_dim_depth())]) if genvars: genvars_instantiation = ''.join([ diff --git a/srdl2sv/components/field.py b/srdl2sv/components/field.py index 3b0872b..ace6c4f 100644 --- a/srdl2sv/components/field.py +++ b/srdl2sv/components/field.py @@ -1189,7 +1189,7 @@ class Field(Component): self.total_dimensions = len(self.total_array_dimensions) # Calculate how many genvars shall be added - genvars = ['[{}]'.format(chr(97+i)) for i in range(len(array_dimensions))] + genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(len(array_dimensions))] self.genvars_str = ''.join(genvars) # Write enable diff --git a/srdl2sv/components/regfile.py b/srdl2sv/components/regfile.py index 24af275..ec6393d 100644 --- a/srdl2sv/components/regfile.py +++ b/srdl2sv/components/regfile.py @@ -120,7 +120,7 @@ class RegFile(Component): self.rtl_footer.append( self.process_yaml( RegFile.templ_dict['generate_for_end'], - {'dimension': chr(97+i)} + {'dimension': ''.join(['gv_', chr(97+i)])} ) ) @@ -128,7 +128,7 @@ class RegFile(Component): self.rtl_header.append( self.process_yaml( RegFile.templ_dict['generate_for_start'], - {'iterator': chr(97+i+self.parents_depths), + {'iterator': ''.join(['gv_', chr(97+i+self.parents_depths)]), 'limit': self.array_dimensions[i]} ) ) @@ -174,7 +174,7 @@ class RegFile(Component): self.dimensions = len(self.array_dimensions) # Calculate how many genvars shall be added - genvars = ['[{}]'.format(chr(97+i)) for i in range(self.dimensions)] + genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(self.dimensions)] self.genvars_str = ''.join(genvars) def create_mux_string(self): diff --git a/srdl2sv/components/register.py b/srdl2sv/components/register.py index b8c07ff..8254eb4 100644 --- a/srdl2sv/components/register.py +++ b/srdl2sv/components/register.py @@ -64,7 +64,7 @@ class Register(Component): for i in range(self.dimensions): self.rtl_header.append( Register.templ_dict['generate_for_start'].format( - iterator = chr(97+i+self.parents_depths), + iterator = ''.join(['gv_', chr(97+i+self.parents_depths)]), limit = self.array_dimensions[i])) # Add decoders for all registers & aliases @@ -82,7 +82,7 @@ class Register(Component): for i in range(self.dimensions-1, -1, -1): self.rtl_footer.append( Register.templ_dict['generate_for_end'].format( - dimension = chr(97+i))) + dimension = ''.join(['gv_', chr(97+i)]))) if self.dimensions and not self.generate_active: self.rtl_footer.append("\nendgenerate\n") @@ -524,7 +524,7 @@ class Register(Component): self.dimensions = len(self.array_dimensions) # Calculate how many genvars shall be added - genvars = ['[{}]'.format(chr(97+i)) for i in range(self.total_dimensions)] + genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(self.total_dimensions)] self.genvars_str = ''.join(genvars) # Determine value to compare address with @@ -532,7 +532,7 @@ class Register(Component): genvars_sum_vectorized = [] try: for i, stride in enumerate(self.total_stride): - genvars_sum.append(chr(97+i)) + genvars_sum.append(''.join(['gv_', chr(97+i)])) genvars_sum.append("*") genvars_sum.append(str(stride)) genvars_sum.append("+")