diff --git a/examples/enums/Makefile b/examples/enums/Makefile
index cd5563d..ea76bfb 100644
--- a/examples/enums/Makefile
+++ b/examples/enums/Makefile
@@ -2,7 +2,10 @@ RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))
 
 .PHONY: clean 
 
-default: $(RTL_TARGETS)
+default: verilog_compile
+
+verilog_compile: $(RTL_TARGETS)
+	verilator -cc -sv $(shell ls srdl2sv_out/*.sv)
 
 srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
 	srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO
diff --git a/examples/hierarchical_regfiles/Makefile b/examples/hierarchical_regfiles/Makefile
index cd5563d..ea76bfb 100644
--- a/examples/hierarchical_regfiles/Makefile
+++ b/examples/hierarchical_regfiles/Makefile
@@ -2,7 +2,10 @@ RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))
 
 .PHONY: clean 
 
-default: $(RTL_TARGETS)
+default: verilog_compile
+
+verilog_compile: $(RTL_TARGETS)
+	verilator -cc -sv $(shell ls srdl2sv_out/*.sv)
 
 srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
 	srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO
diff --git a/examples/interrupt_hierarchy/Makefile b/examples/interrupt_hierarchy/Makefile
index cd5563d..ea76bfb 100644
--- a/examples/interrupt_hierarchy/Makefile
+++ b/examples/interrupt_hierarchy/Makefile
@@ -2,7 +2,10 @@ RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))
 
 .PHONY: clean 
 
-default: $(RTL_TARGETS)
+default: verilog_compile
+
+verilog_compile: $(RTL_TARGETS)
+	verilator -cc -sv $(shell ls srdl2sv_out/*.sv)
 
 srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
 	srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO
diff --git a/examples/parameters/Makefile b/examples/parameters/Makefile
index cd5563d..ea76bfb 100644
--- a/examples/parameters/Makefile
+++ b/examples/parameters/Makefile
@@ -2,7 +2,10 @@ RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))
 
 .PHONY: clean 
 
-default: $(RTL_TARGETS)
+default: verilog_compile
+
+verilog_compile: $(RTL_TARGETS)
+	verilator -cc -sv $(shell ls srdl2sv_out/*.sv)
 
 srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
 	srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO
diff --git a/examples/simple_rw_reg/Makefile b/examples/simple_rw_reg/Makefile
index cd5563d..ea76bfb 100644
--- a/examples/simple_rw_reg/Makefile
+++ b/examples/simple_rw_reg/Makefile
@@ -2,7 +2,10 @@ RTL_TARGETS = $(subst .rdl,.sv,srdl2sv_out/$(shell ls *.rdl))
 
 .PHONY: clean 
 
-default: $(RTL_TARGETS)
+default: verilog_compile
+
+verilog_compile: $(RTL_TARGETS)
+	verilator -cc -sv $(shell ls srdl2sv_out/*.sv)
 
 srdl2sv_out/%.sv: %.rdl $(shell which srdl2sv)
 	srdl2sv $< --out-dir $(shell dirname $@) --stdout-logging INFO