diff --git a/srdl2sv/components/templates/addrmap.yaml b/srdl2sv/components/templates/addrmap.yaml
index 1098a47..dd13524 100644
--- a/srdl2sv/components/templates/addrmap.yaml
+++ b/srdl2sv/components/templates/addrmap.yaml
@@ -67,8 +67,7 @@ module_declaration:
         <<UNINDENT>>
         (
         <<INDENT>>
-        // Clock & Resets
-        input  reg_clk,
+        // Resets
         {resets} 
 
         // Inputs
diff --git a/srdl2sv/components/templates/fields.yaml b/srdl2sv/components/templates/fields.yaml
index 6d98113..8cfce55 100644
--- a/srdl2sv/components/templates/fields.yaml
+++ b/srdl2sv/components/templates/fields.yaml
@@ -1,10 +1,10 @@
 ---
 sense_list_rst:
     rtl: |-
-        always_ff @(posedge reg_clk or {rst_edge} {rst_name})
+        always_ff @(posedge clk or {rst_edge} {rst_name})
 sense_list_no_rst: 
     rtl: |-
-        always_ff @(posedge reg_clk)
+        always_ff @(posedge clk)
 rst_field_assign: 
     rtl: |-
         if ({rst_negl}{rst_name})